This work demonstrates the capability of E-beam probing, combined with optical techniques, to effectively monitor the activity of the IC structures and extract the signals from a 16nm technology device through the silicon backside. We conducted optical probing to localize the area of interest on the device, where we aimed the E-beam probing to gather the signal. Once the target was located, a trench down to the STI level was opened on the device. This enables the use of E-beam probing, which has a much higher resolution than the optical methods.

Mechanical sample preparation is a crucial and indispensable step in modern failure analysis (FA). Traditional methods excel in reducing bulk silicon to thicknesses of several tens of micrometers. However, contemporary demands necessitate sample preparation below 10 µm or even below 5 µm, which is challenging, time-consuming, and requires an expensive toolset and advanced operator expertise. Existing methods, which rely on mechanical components for bulk removal, induce mechanical stress and microcracks that can alter the electrical characteristics of the sample. Maintaining the sample's electrical behavior is essential for accurate FA. This paper introduces a novel approach to sample preparation that employs concepts from wafer-level chemical mechanical polishing (CMP). This method ensures reliable sample preparation without introducing microcracks, accurately halts material removal at the shallow trench isolation (STI) – or deep STI - level, and maintains the sample's electrical functionality. The proposed approach is discussed in detail, including successful thinning of various sample types to the STI level, which were subsequently tested for electrical functionality.

When aiming for extreme thinning of the bulk silicon down to the shallow trench isolation (STI) level, endpoint determination is a challenging task. Here, we present a novel approach providing reliable access to the STI level of single dies. Therefore, we transfer the wafer-based CMP process to be applicable to single dies on a table-top machine. In a first step, the developed process is applied to the whole IC backside simultaneously. Using a highly selective slurry with a material removal ratio from Si to SiO of more than 500:1 ensures that the STI level remains intact. Two types of samples have been prepared for experiments performed for this paper. A 115mm x 80mm flip-chip bonded device with a bulk silicon thickness of 500μm has been prepared to STI level within less than 4 hours.

Contactless probing methods through the chip backside have been demonstrated to be powerful attack techniques in the field of electronic security. However, these attacks typically require the adversary to run the circuit under specific conditions, such as enforcing the switching of gates or registers with certain frequencies or repeating measurements over multiple executions to achieve an acceptable signal-to-noise ratio (SNR). Fulfilling such requirements may not always be feasible due to challenges such as low-frequency switching or inaccessibility of the control signals. In this work, we assess these requirements for contactless electron- and photon-based probing attacks by performing extensive experiments. Our findings demonstrate that E-beam probing, in particular, has the potential to outperform optical methods in scenarios involving static or low-frequency circuit activities.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

This paper compares the three major semi-invasive optical approaches, Photon Emission (PE), Thermal Laser Stimulation (TLS) and Electro-Optical Frequency Mapping (EOFM) for contactless static random access memory (SRAM) content read-out on a commercial microcontroller. Advantages and disadvantages of these techniques are evaluated by applying those techniques on a 1 KB SRAM in an MSP430 microcontroller. It is demonstrated that successful read out depends strongly on the core voltage parameters for each technique. For PE, better SNR and shorter integration time are to be achieved by using the highest nominal core voltage. In TLS measurements, the core voltage needs to be externally applied via a current amplifier with a bias voltage slightly above nominal. EOFM can use nominal core voltages again; however, a modulation needs to be applied. The amplitude of the modulated supply voltage signal has a strong effect on the quality of the signal. Semi-invasive read out of the memory content is necessary in order to remotely understand the organization of memory, which finds applications in hardware and software security evaluation, reverse engineering, defect localization, failure analysis, chip testing and debugging.

This paper provides a detailed analysis on the optical detection of temperature effects in FinFETs via (spectral) photon emission microscopy (SPEM/PEM) with InGaAs detector and electro-optical frequency mapping (EOFM, similar to LVI) for 14/16 nm Qualcomm Inc. FinFETs. It analyzes physical parameters of the FinFETs such as electron temperature and the relation between signal curve and operating condition of the device by photon emission slopes and spectra. The paper also traces device self-heating effects within the FinFETs by means of EOFM signal courses. With EOFM it was possible to detect self-heating effects of the FinFETs providing a further method to estimate device and substrate heating. Results showed that it is possible to obtain valuable device parameter information (for example, electron temperatures and self-heating) via optical investigations (PEM/ EOFM), which are not accessible electrically in modern integrated circuits. This information adds further details to device reliability and functionality approximations.

Modern integrated circuits (ICs) are in permanent risk of hardware attacks on sensitive data. But, proper and affordable protection of the IC backside against Focused Ion Beam (FIB) and optical fault injection attacks is missing. In this work, we investigate a patent [1] that uses p-n junctions as light emitters (forward bias) and detectors. We improved the backside detection mechanism presented in the patent by developing a test structure and adding an optically active layer on the backside as protective element to detect an attacked backside with electrical signals in the IC. The angle dependent reflection provided by the layer acts as the protective function. We demonstrate how the light emission and detection concept is quantitatively working and how the active layer produces a backside layer integrity related signal in the IC which can act as attack indicator. We also show that, due to the weak light emission intensity of silicon and the high excitation current, influences such as multi-angle reflection and stray current are reducing the angle-dependent effect on the signal and have to be taken into account in practical use.

As the Internet of Things, smart factories and autonomous driving increase the demand for low-price radar sensors, the authors address this need by developing a 24 GHz short range radar in standard bulk silicon CMOS technology for mass market production. CMOS technology enables cost reduction and efficient system integration compared to former GaAs and current SiGe solutions. Design for failure analysis (DFFA) is implemented in the low-noise amplifier (LNA) of the radar to identify and compensate process deviations. It consists of scalable capacitor structures and is executed using focused ion beam circuit edit. By doing so, the design specifications of high gain and low noise of the LNA are reliably met at high yield for the desired operating frequency. The presented DFFA method enables a shift in peak gain by 2.5 GHz. It thereby improves gain and noise figure at 24 GHz by 2 dB and -0.2 dB respectively. The resulting optimized LNA achieves a gain of 20 dB and a noise figure of 3.7 dB matching and surpassing other state-of-the-art works in a single prototyping run.

The visible approach of optical Contactless Fault Isolation (VIS-CFI) serves the perspective of application in FinFET technologies of 10 nm nodes and smaller. A solid immersion lens (SIL) is mandatory to obtain a proper resolution. A VISCFI setup with SIL requires a global polishing process for sub-10 µm silicon thickness. This work is the first to combine all these necessary components for high resolution VIS-CFI in one successful experiment. We demonstrate Laser Voltage Imaging and Probing (LVI, LVP) on 16/14 nm technology devices and investigate a focus depth dependence of the LVI/LVP measurement in FinFETs.

Programmable logics, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs), are widely used in security applications. In these applications cryptographic ciphers, physically unclonable functions (PUFs) and other security primitives are implemented on such platforms. These security primitives can be the target of fault injection attacks. One of the most powerful examples of fault injection techniques is laser fault injection (LFI), which can induce permanent or transient faults into the configuration memories of programmable logic. However, localization of fault sensitive locations on the chip requires reverse-engineering of the utilized building blocks, and therefore, is a tedious task. In this work, we propose an automated technique using readily available IC debug tools to map and profile the fault sensitive locations of programmable logic devices in a short period.

This work is a unique solution for enhancing optical failure analysis and optical signal transmission. Optical failure analysis remains to be a vital part of the analysis process, despite shrinking feature sizes and challenging package technologies. The presented optical signal transmission supports the development of photonic integrated circuits. The key component is a Focused Ion Beam (FIB) process which shapes optical lenses out of the sample material leading to an improvement in lateral resolution and signal transmission. Two cases are shown that demonstrate these improvements. The first case is an optical backside analysis in a spatially confined opening of a package where other Solid Immersion Lens (SIL) systems could not be applied. It offers an improvement in spatial resolution by a factor of 2, down to a FWHM of 387 nm. The second case is a novel application for FIB shaped lenses aiming at photonic integrated circuits. This lens is created out of the isolating frontside and improves the grating coupler efficiency by a factor of 4.1.

In this work we present spectrally resolved photon emission microscopy (SPEM) measurements for short-channel FETs acquired through the backside of the Si substrate using InGaAs detector. Two spectrum resolution methods have been used: continuous using a prism and discrete using a set of interference band-pass filters. The photon emission (PE) spectra have been corrected for the background / noise of the detector; they have been calibrated with respect to the system optical transmission function and corrected for the absorption on free carriers in the remaining layer of Si substrate. We discuss all the standardization aspects thoroughly as they are crucial in order to obtain correct device-intrinsic PE spectral information. Finally, we present the spectral results for FET devices operated in various operating conditions.

In this work we present spectrally resolved photon emission microscopy (SPEM) measurements originating from short-channel MOSFETs acquired through the backside of the silicon substrate. Two commonly used detectors have been chosen for the detection of electroluminescence (EL) in the visible and near-infrared spectral regime, namely Si-CCD and InGaAs. As the backside photon emission (PE) inspection is strongly influenced by the absorption of light in a substrate material, the SPEM experiments have been carried out through thinned silicon layers as obtained by mechanical grinding and local focused-ion-beam (FIB) assisted Si material removal. Intrinsic Si absorption (generation of electron-hole pairs) and absorption on free carriers have been modeled to be able to calibrate experimental results and obtain devicerelated PE spectra. The results show no evidences of specific transitions and lead to a conclusion that photon emission from MOSFETs is fully electrical field related.

Optical spatial resolution improvement using local focused ion beam (FIB) assisted silicon material removal was investigated. Two types of test structures were chosen for imaging-resolution characterization to be able to use two ways of measuring resolution. Samples of various remaining bulk silicon thicknesses were prepared and characterized in terms of image quality and spatial resolution. The resulting remaining bulk Si thickness was measured using reflectance spectrometry. Images were acquired using halogen-lamp illumination and reflected light detection using a cooled Si-CCD detector. To investigate the image quality at various wavelengths, a set of interference band-pass filters was applied.