The semiconductor failure analyst’s tool box is a vast and resourceful set of capabilities that more than ever needs meaningful Memory Failure Signature Analysis (Memory FSA) as an important part of that suite. Today, this is driven by advanced process technology nodes that are producing virtually invisible defects to confound manufacturing and reliability. This demands greater attention to characterizing memory failures in order to theorize causes for failure and to implement suitable FA approaches and corrective action plans. Design Based FA (DBFA) techniques aim to extend this philosophy by focusing on a deep understanding of the chip’s Intellectual Property (IP), in terms of both content and architecture. It uses this knowledge to gain important insights into the behavior of the failure that otherwise may have been hidden or unobservable. This disciplined methodology leads to quicker closure for problems through implementing improved test screens, providing recommendations under a closed-loop Design for Manufacturing (DFM) system, enacting process enhancements, or some combination of all these areas. Here we present a clever technique to further aid in the failure signature analysis process and use it as an example for this Design Based FA methodology.

This paper presents decapsulation solutions for devices bonded with Cu wire. By removing mold compound to a thin layer using a laser ablation tool, Cu wire bonded packages are decapsulated using wet chemical etching by controlling the etch time and temperature. Further, the paper investigates the possibilities of decapsulating Cu wire bonded devices using full wet chemical etches without the facilitation of laser ablation removing much of mold compound. Additional discussion on reliability concerns when evaluating Cu wirebond devices is addressed here. The lack of understanding of the reliability of Cu wire bonded packages creates a challenge to the FA engineer as they must develop techniques to help understanding the reliability issue associated with Cu wire bonding devices. More research and analysis are ongoing to develop appropriate analysis methods and techniques to support the Cu wire bonding device technology in the lab.

In this paper, DACS stands for Defects that Affect Chain and System, which could be any type of silicon defects caused by an unintentional interaction between a scan chain signal and a system logic signal. The device could fail scan chain testing or show up as a latent failure in the customer’s system. A novel diagnosis methodology is proposed to locate both ends of a DACS. The proposed algorithm can be generally applied to any type of DACS. Experimental results on industrial chips demonstrate the effectiveness of the proposed method.