Grain size monitor of Al pad is necessary to assure pad quality and electrical performance in IC manufacturing. Currently, the sample is prepared either without pretreatment or with 4.9% HF stain or ion milling before grain size measurement. In this paper, we demonstrate the pretreatment has a pronounced effect on the grain size measurement and the method with ion milling pretreatment shows more reliable results. The mechanism is further discussed.

Failures caused by threshold voltage (Vt) shifts in sub-100nm technology transistors have become very difficult to both analyze and determine the failure mechanism. The failure mechanisms for Vt shifts are typically non-visible for traditional physical analysis methods such as SEM inspection or traditional TEM analysis. This paper demonstrates how nano-probing was used to carefully and fully characterize the Vt shift failure to determine a specific electrical signature for a specific failure mechanism and then with junction stain Transmission Electronic Microscopy (TEM) verify the subtle doping defect affecting the Static Random Access Memory function in the 65nm generation node. Device failure due to a lack of Lightly Dope Drain (LDD) implant induced by an inconspicuous spacer defect was determined to be the root cause of the failure.

The corrosion phenomenon was found at the edge area of bond pad under OM images after dicing saw. Experiment showed that the corrosion was related with the feed speed of dicing saw. From SEM and OM results, there were some abnormal contaminations around the corrosive area. Auger and TEM with EDX system were used to characterize the corrosive region and the related Al pad corrosion mechanism was discussed. In this paper, Cu rich and O rich layers were identified by TEM and EDX, which could be induced by galvanic cell reaction.

In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.

Electron beam assisted platinum film deposition has been found to be an effective method to protect the sample surface for both FIB and TEM analysis. In this paper, the phenomena of electron beam assisted deposition of platinum will be reviewed The results suggest that a 45 nm thick residual Pt film can effectively protects (100) silicon from damage induced by ion beam assisted Pt deposition. A carbon based organic layer under the electron beam assisted Pt has been observed. The mechanism and results on exposed oxide thickness measurements will be discussed. It is suggested that a carbon glue cap be used as a protective layer or polysilicon be deposited in line before submitting the wafer for TEM sample preparation and observation.

It has been reported that a sample prepared by ion beam milling has a sandwich structure with amorphous on two sidewalls and crystal in the middle. In this paper, the sandwich structure of such a single crystal TEM sample was studied experimentally. A novel sample and its fabrication process were reported. The sandwich structure can be observed directly in TEM with this sample. When the crystal layer in monocrystal silicon TEM sample is less than 18 nanometers, or when the sample is thinner than 64 nanometers, the sample will be observed as fully amorphous. Removal of the amorphous layer on the sample sidewalls is crucial to get TEM pictures of better quality.

The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.

In this paper, the deformation mechanism of low K dielectric film under electron beams (E-beams) is discussed, and the effect of film deformation on the development of a low K dielectric film etching recipe is investigated. To provide meaningful data for process development, numerical analysis was used in the failure analysis procedure. A correction factor is formulated to calculate the change in thickness of the low K dielectric film after E-beam exposure. In addition, scanning electron microscope (SEM) settings for imaging low K dielectric films are optimized to minimize deformation.

In this paper the artifacts of additional copper signal induced by the copper grid, one of the most widely used supporting grid for focus ion beam (FIB) prepared TEM sample, is studied. Its influence on both the spot and the line scan energy dispersive spectroscopy (EDS) analyses are described. It was determined that, during line scan analysis, the strength of the copper signal varied between heavy and light elements, which could lead to inconclusive results during the EDS analysis of Cu interconnect structures. Based on the study using nickel support grid, it is concluded that the additional copper signal is a result of electrons scattered by the sample striking the Cu grid.

In this paper, a case of package level reliability test failure was studied. A model of “Slice Defect”, which was identified as the root cause by failure analysis, is introduced. Experiment results are presented to approve that such model is in fact correct and the corrective actions are effective.

Accurate characterization of the nitrogen concentration and distribution in ultra thin nitrided silicon gate oxide plays the same important role as the fabrication technology itself during the development of 90nm and beyond gate oxide manufacturing process. Based on the measurement results of XPS (X-ray photoelectron spectroscopy) as reference, a correlation study was taken between XPS and AES (Auger electron spectroscopy) data in this paper. The study shows that, by optimizing the experiment conditions of AES such as beam energy, beam current and take off angle, and introducing proper corrective factor, AES can be used as a useful and reliable characterization tool during the monitoring measurement of Nitrogen concentration in ultra thin (<2nm) nitrided silicon gate oxide.

In this paper, crystal damage on TEM sample sidewalls induced by FIB milling during sample preparation was studied. A novel method was invented to prepare the sample, which facilitates the direct observation of amorphous layers on the sidewall. The ion beam acceleration voltage is the dominant factor that affects the damaged layer thickness. The measured amorphous thickness is about 23 nanometers at 30Kv and 10 nanometers at 10Kv. The damage layer thickness is constant with different beam currents over the range from 30pA to 1000pA. Amorphous layer thickness also stays constant with the sample tilt angle.

This paper examines copper-interconnect integrated circuit transmission electron microscope (TEM) sample contamination. It investigates the deterioration of the sample during ion milling and storage and introduces prevention techniques. The paper discusses copper grain agglomeration issues barrier/seed step coverage checking. The high temperature needed for epoxy solidifying was found to be harmful to sidewall coverage checking of seed. Single beam modulation using a glass dummy can efficiently prevent contamination of the area of interest in a TEM sample during ion milling. Adoption of special low-temperature cure epoxy resin can greatly reduce thermal exposure of the sample and prevent severe agglomeration of copper seed on via sidewall. TEM samples containing copper will deteriorate when stored in ordinary driers and sulphur contamination was found at the deteriorated point on the sample. Isolation of the sample from the ambient atmosphere has been verified to be very effective in protecting the TEM sample from deterioration.