Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.

This paper is to evaluate the doping profile analysis capability of Scanning Capacitance Microscope (SCM) and Scanning Spreading Resistance Microscope (SSRM) on 30nm Dynamic Random Access Memory (DRAM) devices and apply the SSRM technique on a real case to verify the junction depths of different doping recipes for device performance tuning. The results show SCM can be used on periphery devices in a 30nm DRAM due to they have larger feature size (>90nm). For array devices with minimum feature size (~30nm) in a 30nm DRAM, only SSRM is capable with sufficient spatial resolution and sensitivity to identify the structures and doping profiles. For the real case, SSRM analysis results clarified there is approximate 10nm difference on the junction depth between 2 different doping recipes of samples and the result is consistent with the Technology Computer Aided Design (TCAD) simulation data. In addition, both SCM and SSRM techniques showed the analysis quality does highly rely on the surface cleanness and flatness of samples.

This paper demonstrated the use of curve fitting method on device transfer characteristic curve for device carrier mobility analysis and failure mechanism verification. In the content, a systematic device characterization was performed to identify device failure mode and failure site. Based on physical observations and electrical results, a device gate oxide boron penetration failure mechanism and an unexpected subtle p-type dopant at p-MOS device channel area was conjectured. However, this unexpected p-type dopant was successfully proved by subsequent carrier mobility analysis results, and the gate oxide boron penetration failure mechanism was accordingly verified.

The use of in-situ lift-out combined with focused ion beam milling has become a favorable choice as it offers several indispensable advantages compared to the conventional mechanical and ex-situ lift-out sample preparation techniques. This paper discusses the procedures of the multiple-post in-situ lift-out grids preparation using a dicing saw. In addition, a real case is described to show that the multiple-post in-situ lift-out grids have been successfully applied to failure analysis. The multiple-post in-situ lift-out grids provide more positions and flatter surfaces for TEM sample mounting. The flat surface greatly increases the mounting efficiency and success rate. For the real case application, a thick Al fluoride oxide layer and Al corrosion were found above the Al bond pads, which had NOSP problem, and their neighbor area, respectively.