Embedded cache size has dramatically increased with the advent of Intel Hyper-Threading and Multi-Core Technology, making many of the existing cache test validation method less and less practical, if not obsolete. As a result, the effort to sustain and improve array test quality, which is ever so critical to achieve DPM goals, is becoming a formidable challenge. In this paper, we present a test content validation procedure through novel application of Laser Assisted Device Alteration (LADA), i.e. soft fault injection in state elements, which had proven itself in Itanium® 2 array test quality improvement. While the procedure was originally targeting cache test content, the underlying concept has been successfully deployed to expedite scan test content and fault isolation tool validation.

Precise isolation and resolution of scan chain defects are more critical than ever due to increased reliance on scan-based design to achieve desired test content. At the same time, its diagnosis is becoming more difficult as product design increases in complexity alongside shrinking fabrication processes. In this paper, we present a new scan chain diagnosis procedure that is centered on Load Pass Unload Fail/Load Fail Unload Pass (LPUF/LFUP) and Scan Shift Logic State Mapping (SSLSM) techniques to isolate both stuck-at and timing scan chain faults without the design overhead and defect assumptions of previously proposed methods. More importantly, this procedure is extended to analyze scan chain with multiple defects, which is becoming a more frequent occurrence as process scales down in size.

Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.