In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

Electron-beam induced radiation damage can give rise to large structural collapse and deformation of low k and ultra low k IMD in semiconductor devices, posing great challenges for failure analysis by electron microscopes. Such radiation damage has been frequently observed during both sample preparation by dual-beam FIB and TEM imaging. To minimize radiation damage, in this work we performed systematic studies on every possible failure analysis step that could introduce radiation damage, i.e., pre-FIB sample preparation, FIB milling, and TEM imaging. Based on these studies, we utilized comprehensive technical solutions to radiation damage by each failure analysis step, i.e., low-dose/low-kV FIB and low-dose TEM techniques. We propose and utilize the low-dose TEM imaging techniques on conventional TEM tools without using low-dose imaging control interface/software. With these new methodologies or techniques, the electron-beam induced radiation damage to ultra low k IMD has been successfully minimized, and the combination of single-beam FIB milling and low-dose TEM imaging techniques can reduce structure collapse and shrinkage to almost zero.

Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.