The back-end-of-line (BEOL) structure of current IC devices fabricated for advanced technologies is composed of film stacks with multiple interfaces. The requirement of high interfacial strength is therefore necessary between the different layers in the BEOL stacks to ensure device reliability. To enhance the IC performance for new technologies, inter-level dielectric (ILD) made of SiO2 is replaced by low-k and ultra low-k (ULK) dielectrics, which possess a low dielectric constant but have poor mechanical strength. Therefore, the challenge in maintaining BEOL film stack integrity and reliability becomes even greater for advanced technologies. In this paper, we show failure analysis results on a case study of ULK adhesion failure during the IC manufacturing process. The symptoms of the BEOL failure are due to debris dropping on the wafer during chemical mechanical polishing (CMP) after Cu thin film deposition and failure of focusing at wafer extreme edge during the subsequent photolithography process. Extensive mechanical and chemical analyses were conducted on the ULK and adjacent thin films. It was revealed that the interface of ULK and Silicon Nitride from a suspected problematic machine showed abnormally low adhesion energy and high carbon composition. Troubleshooting on that suspected machine found a clog in the foreline. Based on the failure analysis and machine troubleshooting results, the failure mechanism of the case was discussed.

In this work, delineation of crystal defects in Si by preferential chemical etching (Wright etch) is discussed. Investigation of defects in Si wafers by preferential chemical etching enables the study of various types of crystal defects for large area defect distribution (up to full wafer) and root cause analysis. In the case of dislocation defects, the shapes of etch pits are different for different etching duration. We show the mechanism of the pit shape evolution under preferential etching and suggested the appropriate etching duration for defect type identification with inspection by optical microscopes. The dislocation delineation method has been applied to a case of functional failure of devices caused by abnormal process in Laser Scanning Annealing (LSA). It was shown that the distribution of dislocation defects depends largely on the direction of LSA scan direction. We discuss the relationship between dislocation defect distribution and the density and uniformity of the active-Si patterns as well as possible solutions for elimination of dislocation defects in LSA process.

A case study of Fluorine (F)-outgassing is presented in this paper that caused the corrosion of Aluminum bond pad. It will be shown that the source of F-contamination is not the typical residue left behind after the passivation etch with Fluorine-based gas chemistry and the subsequent removal of the etch polymer generated with solvent (chemical) clean. Rather, it is introduced as a result of F-outgas over a period of time from the intermetallic dielectric (IMD) film, fluorosilicate glass (FSG), during the post-fab wafer storage. The methodology used in our failure analysis (FA) lab to identify and characterize this type of failure mode is presented in the paper.

In this paper, a comprehensive analysis methodology for gate oxide integrity (GOI) failure using combined FA techniques is proposed. The current method integrates the failure analysis flow we previously reported with a new flow proposed in this paper. The method is applicable to a wide range of GOI failure cases and has been used in analyzing many product wafers with GOI failure. In particular, there is one wafer with GOI failure that results from known failed process machines. This wafer could be readily analyzed with this new method to identify the root causes. The newly proposed flow is based on our previous report on GOI failure analysis, but the detection limit of contamination elements was significantly improved. The enhancement of detection limit is mainly attributable to the utilization of Vapor Phase Decomposition and Inductively Coupled Plasma Mass Spectrometry (VPD ICP-MS). The ICP-MS technique is highly sensitive and capable of simultaneously measuring a large number of elements at very low concentration level in the range of ppb (part per billion) to ppt (part to trillion). This enhanced sensitivity enables effective investigation of contamination caused by specific machines. A case study of GOI failure investigated by the proposed new method will be discussed in detail. In the study, Al, Fe, Mo and Sn contamination from a suspected tool were detected by ICPMS, followed by confirmation by Secondary Ion Mass Spectrometry (SIMS) on the affected product wafers. Failurepart isolation investigations of the affected diffusion furnace revealed that the root cause of the failure is due to a defective gas flow valve.

Wire bonding continues to remain as the dominant chip interconnect technology in the far backend process, regardless of the shrinkage of microchip Al bond pad size and the increase in the number of I/O connections in the modern ICs. The reliability of IC devices is directly affected by the quality of adhesion between wire bond and microchip Al pad. Many factors, such as the wafer fab process residue and corrosion, creep-induced wire breakage and electrostatic damage, may result in poor adhesion. In this paper, we show a p-channel Field-Effect Transistor (pFET) failure caused by a mismatch in the bond pad size and the wire bond diameter as well as electrostatic damage during wire bonding. The failure analysis results, failure mechanism and the design rule of microchip Al bond pad in wafer fabrication are discussed. FA investigations were performed on the high gate leakage (nA to mA level) issue in the packaged pFET. It was found that two major factors contributed to the failure, namely mechanical and electrostatic damage. The mechanical damage was mainly due to incompatible Al pad size and bond wire diameter. More specifically, in the failed device, the bond wire diameter was larger than half size of the bond pad opening, contrary to the general design rules of wire bonding. The failure to adhere to the design rule resulted in the device failure. In addition, the electrostatic damage during wire bonding resulted in defects of poly Si/gate oxide and thus the high gate leakage. In this paper, the FA results, failure mechanism of the high gate leakage and the bond pad design rule will be discussed. Also, it will be demonstrated that to achieve good bonding quality and eliminate mechanical and ESD damage the diameter of the bond wire should be equal to or smaller than half of the bond pad opening.