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Charles Petri
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Proceedings Papers
ISTFA2024, ISTFA 2024: Tutorial Presentations from the 50th International Symposium for Testing and Failure Analysis, o1-o83, October 28–November 1, 2024,
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Presentation slides for the ISTFA 2024 Tutorial session “Advanced FIB/SEM Sample Preparation and Analysis Techniques (2024 Update).”
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 403-410, November 12–16, 2023,
Abstract
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In this work, we present three case studies that highlight the novelty and effectiveness of using multiple plasma FIB trenches to simultaneously access multiple metal layers for nanoprobing failure analysis. Multilayer access enabled otherwise impossible two-tip current imaging techniques and allowed us to fully characterize suspect logic gate transistors by exposing internal nodes, while preserving higher metal inputs and outputs. The presented case studies focus on late node planar and established FinFET technologies. The delayering techniques used are not necessarily technology dependent, but highly scaled and advanced processes generally require smaller trench areas for multilayer access. The minimum trench dimensions are limited by ion beam imaging resolution and trench-nanoprobe tip geometry.
Proceedings Papers
ISTFA2023, ISTFA 2023: Tutorial Presentations from the 49th International Symposium for Testing and Failure Analysis, m1-m58, November 12–16, 2023,
Abstract
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Presentation slides for the ISTFA 2023 Tutorial session “Advanced FIB/SEM Sample Preparation and Analysis Techniques.”
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 228-237, November 5–9, 2017,
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We present an upgraded time-resolved LADA system, with a 25ps pulsed laser, integrated into a commercial laser scanning microscope used in failure analysis. We demonstrate the use of this system on 14nm/16nm finfet devices.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2009) 11 (2): 30–34.
Published: 01 May 2009
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This article presents a case study involving flash memory bit failures characterized by threshold voltage changes due to positive gate disturb stress. An inconsistency in failing bit behavior, which was found to be dependent on the test mode, was explored to provide an electrical explanation for the failure. The underlying defect was isolated and subsequently identified by physical analysis.