The result of applying normal xenon ion beam milling combined with patented DX chemistry to delayer state-of-theart commercial-grade 14nm finFETs has been demonstrated in a Helios Plasma FIB DualBeam™. AFM, Conductive-AFM and nano-probing with the Hyperion Atomic Force nanoProber™ were used to confirm the capability of the Helios PFIB DualBeam to delayer samples from metal-6 down to metal-0/local interconnect layer and in under two hours produce a sample that is compatible with the fault isolation, redetection, and characterization capabilities of the AFP. IV (current-voltage) curves were obtained from representative metal-0 contacts exposed by the PFIB+DX delayering process and no degradation to device parameters was uncovered in the experiments that were run. Compared to mechanically delayering samples, the many benefits of using the PFIB+DX process to delayer samples for nano-probing were conclusively demonstrated. Such benefits, include sitespecificity, precise control over the amount of material removed, >100μm square DUT (device under test) area, nm-scale flatness over the DUT area, nm-scale topography between contacts and the surrounding ILD, uniform conductivity across the DUT area, all with no obvious detrimental effects on typical DC device parameters measured by nano-probing.

Good control over beam and chemistry conditions are required to enable uniform delayering of advanced process technologies in the FIB. The introduction of newer, thinner and more beam sensitive materials have made delayering more complicated. We shall introduce a new chemistry for device delayering and present results from both Ga and Xe ion beams showing its improvement over existing chemistries.

Metal and dielectric depositions using Xe+ plasma FIB tools are reported and comparisons are made to depositions performed with conventional Ga+ FIB tools. Xe+-deposited Pt had a resistivity of 1250 ± 360 μΩ·cm, similar to the typical range of 1000-2000 μΩ·cm reported for Ga+-deposited Pt. Xe+-deposited dielectric depositions using HMCHS/O2 precursors had an average resistivity of 1.27 x 1019 μΩ·cm (at ± 10V electrical bias), compared to a resistivity of 1.05 x 1014 μΩ·cm for similar Ga+-deposited dielectric films. A comparison between HMCHS/O2 and TMCTS/O2 dielectric depositions was performed for Ga+ systems, and the HMCHS/O2 depositions were found to be orders of magnitude more resistive than the TMCTS/O2 depositions. The experimental difficulties associated with measuring extremely high-resistance films are also briefly discussed.

FIB column performance can be difficult to evaluate, and the traditional metrics of imaging resolution and minimum spot size give little indication of how a FIB system will perform its intended daily tasks. A series of supplemental FIB performance tests is proposed to quantify “milling acuity” under real-world conditions. A quantitative measuring scheme for evaluating the quality of High Aspect Ratio (HAR) vias is proposed, and an example is shown in which the HAR measuring scheme can be used for process development.

The sample preparation required for a typical backside circuit edit (CE) is a significant barrier for some labs, as it requires specific hardware and considerable operator expertise. There are also instances in which it is not possible to mechanically thin the silicon in the typical fashion. This paper addresses the possibility of backside CE be performed on full-thickness silicon devices and the possibility of skipping off the thinning step, as well as the advantages and disadvantages of this approach. Sample trenches are shown, and trenching optimization experiments are described. The paper addresses the issues of navigation, including IR imaging through full-thickness silicon, and how it depends on the sample doping levels. Finally, it presents data on a novel navigational technique that can be employed to improve targeting accuracy. The paper shows that backside CE on full-thickness silicon devices is possible despite the challenges.

Focused ion beam (FIB) tools are used to perform "circuit edit," (CE), in which existing integrated circuit devices are modified to create prototype devices that simulate potential mask changes. Although ion milling at low keV is common in TEM sample preparation, the technique has not become commonplace for CE applications. This is because most commercial FIB systems are optimized for either 30 or 50 keV. Recent work in the laboratories of FEI and Intel have attempted to apply low keV FIB processing to cutting small copper lines on advanced IC devices. The majority of this paper focuses on water-assisted, low keV copper etching. Secondary objectives of this work are to raise general awareness among FIB users of the potential benefits of low keV processing, to speculate on the physical mechanisms involved, and to discuss some of the technical difficulties associated with low keV FIB operation.

For most advanced semiconductor products, the preferred methodology for achieving Focused Ion Beam (FIB) circuit modification and node access is through the backside of the chip. The high density of interconnect wiring and the presence of C4 solder bumping has made complex edits virtually impossible with conventional frontside techniques. IBM has developed a set of procedures for performing backside edit on circuits built using the Silicon-On-Insulator (SOI) process. While the basic approach and techniques parallel many of the established practices developed for handling transistors built in conventional bulk silicon, there are a number of key and critical differences. In this paper, we will address the basic instruction set developed for successful FIB work on SOI product. This will include backside silicon surface preparation, charge control, endpointing during high volume silicon removal, global and local coordinate lock techniques, floor voltage contrast phenomena, floor preparation and preservation, fill pattern issues and advantages, and finally the target structure alignment, access, connection and/or removal. Post process bake and handling will also be discussed.

Focused Ion Beam (FIB) success has become more difficult as microchip process technology advances, requiring new techniques for damage control both during the microsurgery procedure and before the finished product can be electrically tested. Ultra thin gate dielectrics, shallower junctions, less ‘white space,’ and new materials surrounding active devices all create additional challenges for imaging, targeting, controlling instantaneous charge damage, and the removal of residual implanted charge. On the macro level, global thinning of bulk silicon housed in hybrid packages is causing new problems with thermal management and mechanical stress. Techniques and procedures used to control electrostatic discharge type damage become ever more critical when working on poorly buffered or isolated device elements, especially from the backside. Implanted gallium and residual charge perturb electrical characteristics, and must be dispersed prior to power-up thru carefully controlled bake steps. Left in place, these FIB-induced perturbations are likely to cause poor functionality or even latchup. The mechanical rigidity and thermal dissipation properties of newer, complex package types must also be restored post-FIB, otherwise cracked silicon or a thermal overload event might be the outcome. In this paper, we will attempt to address some of the common causes of FIB-induced failure on newer silicon and package technologies, and how they might be overcome. FIB techniques and preparatory processes must continue to evolve in order to deal effectively with the problems of direct beam damage, residual charge elimination, and sample stress management.