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1-4 of 4
Caiwen Yuan
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Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 574-579, November 6–10, 2016,
Abstract
View Papertitled, Improved Method of ROI Encapsulation during Axis Conversion of Cross-Sectional S/TEM Lamellae
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for content titled, Improved Method of ROI Encapsulation during Axis Conversion of Cross-Sectional S/TEM Lamellae
Defect localization has become more complicated in the FinFET era. As with planar devices, it is still generally possible to electrically isolate a failure down to a single transistor. However, the complexity of certain FinFET devices can lead to ambiguity as to the exact physical location of the defect. The default technique for isolating the defect location for this type of device is to start with a plan view S/TEM lamellae. Once the defect is located in plan view, the lamellae can be converted to cross-section (if necessary) for further characterization. However, if the defect is not detectable in plan view S/TEM analysis, an alternative approach is to examine the device in cross-section along either the x- or y- axis. Once the defect is located in the initial cross-sectional lamellae, it can be converted to the orthogonal axis if the initial cross-sectional lamellae did not provide adequate information for characterization. However, in converting a cross-sectional lamellae to the orthogonal axis, the initial lamellae must be exceedingly thin due to the dimensions of devices on 1x nm FinFET technologies, else other structures on the sample can obscure the view in the S/TEM. This can lead to structural integrity (warping) issues for the converted lamellae. In this paper, a novel solution to the warping issue is presented.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 474-479, November 9–13, 2014,
Abstract
View Papertitled, Application of Passive Voltage Contrast (PVC) to Dual Beam Focused Ion Beam (FIB) Based Sample Preparation for the Scanning/Transmission Electron Microscope (S/TEM)
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for content titled, Application of Passive Voltage Contrast (PVC) to Dual Beam Focused Ion Beam (FIB) Based Sample Preparation for the Scanning/Transmission Electron Microscope (S/TEM)
The modern scanning transmission electron microscope (S/TEM) has become a key technology and is heavily utilized in advanced failure analysis (FA) labs. It is well equipped to analyze semiconductor device failures, even for the latest process technology nodes (20nm or less). However, the typical sample preparation process flow utilizes a dual beam focused ion beam (FIB) microscope for sample preparation, with the final sample end-pointing monitored using the scanning electron microscope (SEM) column. At the latest technology nodes, defect sizes can be on the order of the resolution limit for the SEM column. Passive voltage contrast (PVC) is an established FA technique for integrated circuit (IC) FA which can compensate for this resolution deficiency in some cases. In this paper, PVC is applied to end-pointing cross-sectional S/TEM samples on the structure or defect of interest to address the SEM resolution limitation.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 202-205, November 6–10, 2005,
Abstract
View Papertitled, Method of Failure Site Isolation for Flash Memory Device Using FIB, Passive Voltage Contrast Techniques
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for content titled, Method of Failure Site Isolation for Flash Memory Device Using FIB, Passive Voltage Contrast Techniques
Current VLSI devices have very complicated circuit designs and very small feature size. As a result, fault isolation on failing devices becomes a more and more challenging task. Although backside photoemission technique is commonly used to detect the failure site covered with multiple metal layers, it has the disadvantages of more time consumption and less success rate. Without a localized failure site, it will be very difficult, sometime even impossible, to find the physical evidence for the failures. This article describes a method that has been successfully used for isolating the wordline leakage on a memory FLASH device using FIB cutting and passive voltage contrast on the leaky wordline. The concept of this article is not just limited to this application; rather it can be used for all similar types of fault isolation work for other applications.
Proceedings Papers
ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 183-188, November 3–7, 2002,
Abstract
View Papertitled, Application of Focused Ion Beam in Debug and Characterization of 0.13 µm Copper Interconnect Technology
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for content titled, Application of Focused Ion Beam in Debug and Characterization of 0.13 µm Copper Interconnect Technology
Focused Ion Beam (FIB) has been widely accepted in circuit modification and debugging of new chips and process technologies [1]. It has the advantages of rapid confirmation of design fixes and reducing the cost and time to build new masks. In this paper, we will describe the latest application of FIB to debugging Static Random Access Memory (SRAM) test chips processed on a dense copper metallization technology. Examples of finding leaky capacitors will be given. Individual transistors in the cell array have also been “fibbed” and characterization curves were measured. We compare the measurement with the SPICE simulation and discuss possible damage to the underlying transistors during FIB pad creation. Resistors in the periphery circuit were fibbed and measured with two and four point probes. Contact resistance was characterized and compared to that of Al interconnects. Example of finding problem vias with the help of cross-section and voltage contrast is given.