The topic of this work is the sequential use of Solid Immersion Lenses (SILs), created in bulk silicon in less than 20 minutes of processing time, using a focused ion beam and a bitmap milling process. Fibbed SILs can be removed by polishing, and the silicon back surface resumes a perfect planar shape for further backside analysis or the creation of more SILs. The influence of the progressively thinner sample thickness on the magnification of the SIL was analyzed. As fibbed SILs in this work are about 1.4 µm thick and have an additional magnification of 2.4, a second process after removal has been found to decrease magnification not more than 20%. The presence of interference rings in the SIL image could be almost completely removed by anti-reflective coating. Photon emission microscopy, performed using fibbed SILs, allowed to clearly distinguish between sources that were separated by 240 nm wide structures.

This work describes how Solid Immersion Lenses (SILs) can be created in bulk silicon using a focused ion beam and a bitmap milling process. The optical properties are in good agreement with the expected results for the achieved lens geometries. An improvement in lateral spatial resolution by a factor of 1.8 and in image contrast by 170 % for backside analysis is demonstrated. The presented SILs are 32 µm in diameter with a field of view of about 10 μm. This process can be an alternative when a regular SIL placement on the chip is impossible or complex. The advantages of this method are the use of a single kind of material (no air gaps and no additional lens material with different n value), the ability to precisely position the SIL on the circuitry and the fact that a SIL may be created in less than twenty minutes of processing time.

Novel Fabry Perot [1] fringe analysis techniques for monitoring the etching process with a coaxial photon-ion column [2] in the Credence OptiFIB are reported. Presently the primary application of these techniques in circuit edit is in trenching either from the front side or from the backside of a device. Optical fringes are observed in reflection geometry through the imaging system when the trench floor is thin and semi-transparent. The observed fringes result from optical interference in the etalon formed between the trench floor (Si in the case of backside trenching) and the circuitry layer beyond the trench floor. In-situ real-time thickness measurements and slope correction techniques are proposed that improve endpoint detection and control planarity of the trench floor. For successful through silicon edits, reliable endpoint detection and co-planarity of a local trench is important. Reliable endpoint detection prevents milling through bulk silicon and damaging active circuitry. Uneven trench floor thickness results in premature endpoint detection with sufficient thickness remaining in only part of the trench area. Good co-planarity of the trench floor also minimizes variability in the aspect ratios of the edit holes, hence increasing success rates in circuit edit.

Results of experimental studies are presented which address a concern that gallium staining from FIB imaging during backside editing might degrade IR navigation as well as signal acquisition during probing of flip chips by such techniques as Picosecond Imaging Circuit Analysis (PICA) and Laser Voltage Probing (LVP). Although optical transparency does depend on gallium implantation dose, Ga staining is, however, not necessarily a limitation to the implementation of photon optical tools in the debug laboratory. Comparisons are made on the results from devices under the following conditions: with and without an anti-reflective (AR) coating, with and without XeF2 enhancement during FIB etching, and with confocal laser scanning microscope (CLSM) imaging and CCD-based IR microscope imaging.