Due to relentless down scaling of device geometries, failure analysis is getting more and more complex. As a matter of fact, the success rate of Thermal Laser Stimulation (TLS) techniques drops significantly for 90/65 nm CMOS devices because of the lack of x, y and z accuracy. In our aim to improve the TLS based fault isolation method, we have studied thermal time-constant signatures using a Modulated Optical Beam Induced Resistance Change (MOBIRCH) technique that may provide accurate x and y submicron resolution as well as depth or z-information of defects in the interconnection part of devices. Both Modeling and measurement results indicate that OBIRCH signal phase shifts and heat-up & cool-down time constants indeed do correlate with the location, dimensions and density of the structures studied.

Even though failure analysis performed with a latest generation Phemos 2000 Optical Beam Induced Resistance Change (OBIRCH) tool has given excellent results for 120nm and 90nm technology developments, the limitations of tool and technique become apparent when used for the 65nm technology node and beyond. This article discusses the use of a pulsed laser in combination with a lock-in amplifier for OBIRCH-based fault isolation in latest generation CMOS devices. Using such set-up with appropriate settings for laser pulse frequency, scan speed, and phase shift off-set, a ten-fold signal-to-noise ratio gain is achieved. This improved S/N ratio allows detecting faulty circuitry with higher sensitivity and isolating faults that cannot be detected with the traditional OBIRCH set-up. Various case studies on latest technology devices are presented to illustrate the interest of adding the lock-in capability to the standard OBIRCH tool.

IC manufacturers, among other things, have to define a global failure analysis (FA) strategy that is best adopted to the challenges associated to the introduction of the 90 and 65 nm CMOS technologies. This article reviews the existing FA techniques and then describes an FA strategy that is aiming at fast, efficient, and economic learning in the latest 120-65 nm CMOS technologies. The strategy is based on a well-balanced mix and usage of in-line defectivity data, voltage contrast analyses, SRAM bitmap analysis results, OBIRCH fault isolation, and various advanced physical characterization techniques. A SRAM bitmap strategy has demonstrated to be very effective in driving most relevant process improvements, and also OBIRCH applied to parametric test structures has helped significantly in identifying major yield detractors.

Given the ever increasing complexity of conducting failure analysis on today's latest generation manufacturing processes, the authors have investigated and implemented OBIRCH techniques into process development failure analysis practices. They describe their applications of OBIRCH to 120, 90, and 65 nm samples and their methods for interpreting the results. The OBIRCH technique has the ability to address faults within most structure types and quickly give information on a number of failing sites. It has proven itself as a necessary tool for failure analysis at advanced technology nodes, where fault characterization is getting difficult due to extremely small critical dimensions. The results obtained using the OBIRCH tool have been excellent on 120nm and initial 90nm results. The authors have not yet analyzed enough 65nm samples to form any type of conclusion regarding the tools ability at this technology node.