In this paper, we present methods for targeted silicon thinning by contour milling to overcome challenges associated with thinning large devices to under 5 µm remaining silicon thickness. Implementation of these techniques are expected to improve the yield of ultra-thin sample preparation and thermal stability of the device through electrical failure analysis for subsequent physical failure analysis. Using a computer numerical controlled milling system, the natural device bow is exploited to thin a specified area of interest by stage tilting before 2D milling. To target a larger area of interests, contour maps are rigged to thin an area preferentially while remaining compatible with existing workflows. Electrical testing have found improved thermal stability of the locally thinned samples over globally thinned samples.

Magnetic current imaging (MCI) using superconducting quantum interference device (SQUID) and giant-magnetoresistive (GMR) sensors is an effective method for localizing defects and current paths [1]. The spatial resolution (and sensitivity) of MCI is improved significantly when the sensor is as close as possible to the current paths and associated magnetic fields of interest. This is accomplished in part by nondestructive removal of any intervening passive layers (e.g. silicon) in the sample. This paper will present a die backside contour-milling process resulting in an edge-to-edge remaining silicon thickness (RST) of < 5 microns, followed by a backside GMR-based MCI measurement performed directly on the ultra-thin silicon surface. The dramatic improvement in resolving current paths in an ESD protect circuit is shown as is nanometer scale resolution of a current density peak due to a power supply shortcircuit defect at the edge of a flip-chip packaged die.

High resolution laser imaging, using high numerical aperture (NA) solid immersion lens (SIL) for backside fault isolation imposes stringent sample preparation requirements; as a result of the short focal length of SIL, a die must be thinned to a targeted thickness with less than a ±5 μm silicon thickness variation across the entire die. Flip chip packaged dice suffer from warpage due to various package sizes and substrate thicknesses. Such broad spectrums of part geometries pose a great challenge to meet such silicon planarity requirements. As relaxation of the packaged silicon during polishing causes the warpage profile to change dynamically and unpredictably throughout the thinning process, it has become an added challenge to meet the stringent sample preparation requirements. To overcome the stochastic nature of this problem, a two-step polishing recipe consisting of computer numerical control (CNC) mechanical milling and polishing processes has been developed to achieve sufficient silicon thickness uniformity to enable SIL imaging across an entire silicon chip as large as approximately 20 mm x 15 mm.