This article presents a step-by-step sample preparation method for the cross sectioning of silicon die in a ceramic package without the need for die removal or epoxy encapsulation. The sample preparation includes sawing the package, sample mounting to the polishing stub, and FIB cutting the area of interest and SEM Exam. In addition, a discussion on an automatic polishing method is included. This method is applicable for a broad range of silicon (Si) die package technologies and has also been successfully used on "TSOP" and state-of-the-art microprocessor packages which include the "organic" substrate, the Si die, and the massive copper die lid. The entire failure analysis is done at room temperature, eliminating any questions about sample preparation artifacts. Because the sample is imaged in the SEM at 90 degrees, much improved layer detail and voids microstructure is present in the final image.

The essential role of the material analysis laboratory in modern IC production is confirmed by the scale of the investment made in such facilities. The laboratories are part of the initial design of the fab and are well staffed and superbly well equipped. There are many factors which drive this investment, but perhaps the most compelling is the realization that the materials analysis lab is required to support early fab start-up, support production needs, and to pursue process development. During this talk, examples of each of these functions will be presented. The metrology of IC production is highly varied, and the implementation of this metrology varies widely company-to-company and even within any given company. The balance of in-fab vs out-offab measurements is of considerable importance and will be discussed in detail during this talk. Pertinent examples of contamination analysis and defect review will be presented. Looking ahead to 100 and 70nm nodes, the imaging requirements are daunting and will require scanning electron microscopes with astoundingly high resolution. Remembering that the physical gate length in a modern microprocessor is approximately one half the technology node size, it is clear that imaging 35nm transistors at 500KX will be required. Examples of state-of-the-art SEM, TEM and STEM will be presented as a "look-ahead" into the imaging requirements of the sub 100nm technology generations. The introduction of exotic materials such as high and low K oxides and ultra-thin barriers present special challenges and will spur a lively debate as to which measurements are needed, which measurements can/should be taken in the fab, and, of course, the turnaround time and cost? The rush to early process transfer and early production has given rise to the concept of "concurrent process development and transfer", where the new process flow is transferred to the megafab, almost in its infancy. In this case, the role of the materials analysis lab is expanded to directly aid "next generation" process development. As can be seen from the discussion above, the importance and linkage between Materials Analysis and IC process control has never been greater.