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Brian Lai
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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 213-216, October 28–November 1, 2024,
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This paper presents a novel method for determining the Z-depth location of short circuit defects in flip chip packages using lock-in thermography (LIT). The approach analyzes phase shift values from localized hot spots using the LIT system's "Image Statistics" feature, specifically focusing on phase "mean" values at specific lock-in frequencies. Through extensive testing on 2.5D stacked silicon interconnect technology (SSIT) packages exhibiting short failures, we established a strong correlation between phase mean values and the vertical location of defects. This technique's reliability was validated through both physical analysis and non-destructive verification methods, demonstrating its effectiveness as a precise diagnostic tool for complex semiconductor packages.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 120-124, October 30–November 3, 2022,
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Infrared lock-in thermography systems are frequently utilized for non-destructive failure analysis of integrated circuits due to sensitivity of the thermal detector to small temperature changes from electrical activity. This thermal sensitivity can also be leveraged for design verification and debug of device thermal management via absolute temperature mapping. The application of temperature mapping to a device under test (DUT) that requires boards and sockets, such as in tester based applications, has traditionally been challenging, due to the requirement that the DUT not be moved and the difficulty of heating the DUT through the thermal mass of the boards and sockets to which the DUT is mounted. This paper describes a proposed alternative single-temperature in-situ calibration method to eliminate the need for a heated thermal chuck for absolute temperature mapping. Preliminary results are promising and show that the new alternative single-temperature in-situ method results in temperature measurements within 1 °C close to room temperature and within 2.5 °C at elevated temperatures up to approximately 75 °C, as compared to the 1 °C accuracy of the current standard two-temperature in-situ method. While this alternate method is not as accurate as the standard two-temperature in-situ calibration method, the fact that it can be performed at a single room temperature means that it enables absolute temperature mapping for use cases requiring boards or socketed DUTs, as is the case for tester applications. An example characterization of a DUT utilizing varying clock signal inputs shows the added flexibility and ease of setup that the alternative single-temperature workflow brings, creating new opportunities for use-cases such as boards and testers where the use of a heated thermal chuck is not viable.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 12-16, November 15–19, 2020,
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Correlation across applications and imaging platforms is essential and brings increased insurance for fault isolation in advance of destructive imaging. This paper demonstrates an approach for a detailed advanced packaging defect isolation and analysis workflow. To determine the effectiveness of the proposed workflow, a 28nm flip-chip was used as a test vehicle. By using this workflow, the yield in determining the fault location has increased from 60% to over 85%. To further improve the result, a surface charging mitigation scheme was used and the resulting measured correlative offset between the two systems was found to be less than 10um. This creates novel opportunities in reducing the size of the cross-section and increasing the overall throughput to find the defect, with high confidence. This workflow creates unique abilities in fault localization and analysis as it can detect both opens and shorts between the different techniques that are employed.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 1-8, November 10–14, 2019,
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Lock-in thermography (LIT) has been successfully applied in different excitation and analysis modes including classical LIT, analysis of the time-resolved temperature response (TRTR) upon square wave excitation and TRTR analysis in combination with arbitrary waveform stimulation. The results obtained by both classical square wave- and arbitrary waveform stimulation showed excellent agreement. Phase and amplitudes values extracted by classical LIT analysis and by Fourier analysis of the time resolved temperature response also coincided, as expected from the underlying system theory. In addition to a conceptual test vehicle represented by a point-shaped thermal source, two semiconductor packages with actual defects were studied and the obtained results are presented herein. The benefit of multi-parametric imaging for identification of a defect’s lateral position in the presence of multiple hot spots was also demonstrated. For axial localization, the phase shift values have been extracted as a function of frequency [4]. For comparative validation, LIT analyses were conducted in both square wave and arbitrary waveform excitation using custom designed and sample-specific stimulation signals. In both cases result verification was performed employing X-ray, scanning electron microscopy (SEM) and energy dispersive x-ray (EDX) as complementary techniques.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 17-21, October 28–November 1, 2018,
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Lock-in thermography (LIT) phase data is used to generate phase shift versus applied lock-in frequency plots to estimate defect depth in semiconductor packages. Typically, samples need to be tested for an extended time to ensure data consistency. Furthermore, determining the specific point on the thermal emission site to collect data from can be challenging, especially if it is large and dispersive. This paper describes how the use of new computational algorithms along with streamlined and automated workflows, such as self-adjusting thermal emission site positioning and phase measurement auto-stop, can result in improvements to data repeatability and accuracy as well as faster time to results. The new software is applied to generate the empirical phase shift versus applied lock-in frequency plot using 2.5D IC devices with known defect location. Subsequently, experimental phase shift data from reject 2.5D IC devices with unknown defect locations are obtained and compared against the empirical phase shift plot. The defect Z-depth of these devices are determined by comparing where the experimental phase shift data points lies with respect to empirical phase shift plot and validated with physical failure analysis (PFA).