In this paper, we propose an advanced failure analysis method for specifying the location of gate-related fails in the High-k Metal Gate (HKMG) MOSFET. The test sample for this experiment is the sub-15nm technology DRAM (Dynamic Random Access Memory) which consists of high speed HKMG transistors. In terms of HKMG transistors, the modification of gate materials and process schemes provoke the various gate related failures in DRAM which makes it more difficult to examine the sample with conventional analyzing methods. So, IDD3P measurement methods along with dynamic Hot Electron Analyzer (HEA) were employed as an advanced fault localization method. IDD3P measurement data provides word-line (WL) dependent failure types which distinguishes the gate-related failures from other irrelevant failures. From the dynamic HEA with the MAGNUM tester, the accurate failure sites can be obtained. Newly combined two analytical methods that we present in this paper are effective in localizing the failure sites more accurate than previously suggested methods.

We propose an unbiased electrical fault isolation methodology for locating gate oxide breakdown failures in MOSFETs. The test vehicle involves a sub-15nm technology DRAM device which failed due to time-dependent dielectric breakdown (TDDB). This methodology introduces an implementation of Optical Beam Induced Resistance Change with no applied external bias (zero input voltage). From OBIRCH analysis, a change in current was achieved near failure site. This principle was explained based on Seebeck effect and equivalent circuit modeling of the MOSFET drain within Seebeck generator. A physical cross section using the Focused Ion Beam (FIB) revealed a gate oxide breakdown along the location of the OBIRCH spot, illustrating the benefit of an unbiased fault isolation to preserve the failure mechanism. This study proves that gate oxide breakdown site can still be located even with no external voltage applied, preserving the device condition of nanoscale DRAM, and eliminating the chances of altering the failure mechanism as a result of the applied external voltage stress.