With the development of semiconductor technology and the increment quantity of metal layers in past few years, backside EFA (Electrical Failure Analysis) technology has become the dominant method. In this paper, abnormally high Signal Noise Ratio (SNR) signal captured by Electro-Optical Probing (EOP)/Laser Voltage Probing (LVP) from backside is shown and the cause of these phenomena are studied. Based on the real case collection, two kinds of failure mode are summarized, and simulated experiments are performed. The results indicate that when a current path from power to ground is formed, the high SNR signal can be captured at the transistor which was on this current path. It is helpful of this consequence for FA to identify the failure mode by high SNR signal.

In recent years, laser reflectance modulation measurements are widely used in failure analysis. Among them, EOFM (Electron-Optical Frequency Mapping) technique is easy to operate and very practical. In this article, some images with abnormal EOFM phenomena and their corresponding defects are showing up, the causes of those abnormal EOFM phenomena are also pointed out. They prove that EOFM function is very effective for discovering open or high-impedance defects on metal trace and pinpointing short-circuit defects. In addition to the two aspects above, there are also some abnormal EOFM phenomena we couldn’t explain perfectly. We studied one of them and proposed two possible causes of the anomaly. After simulation experiment and calculation, it could be basically determined that the abnormal EOFM phenomenon was caused by the substrate noise current.

In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

High gate to source/drain (S/D) leakage was observed at both failed pins and ET structures with random failure signatures. Detailed TEM failure analysis revealed an abnormal thin Nitrogen-rich nitride layer along the poly gate which extended to the S/D regions. Along the abnormal nitride layer, appreciable Arsenic (As) segregation occurred. The segregated As dopants at these interfaces may form a continuous conducting path, accounting for the gate to S/D leakage mechanism. The preferable As segregation at the Silicon nitride interface may be related to a vacancy-assisted As diffusion process.