The semiconductor industry is no longer driven purely by performance. Miniaturization, increased functionality, low latency and high bandwidth requirements are becoming more important. Furthermore, as Moore’s law scaling becomes more difficult and costly, innovations in packaging technologies through heterogeneous integration are being adopted rapidly to meet these demands. This paper discusses how defects in InFO (Integrated Fan-Out) wafer level multi-die semiconductor packages can be successfully root caused and describes the challenges faced when doing failure analysis of such packages.

3D X-ray microscopy (XRM) is an effective highresolution and non-destructive tool for semiconductor package level failure analysis. One limitation with XRM is the ability to achieve high-resolution 3D images over large fields of view (FOVs) within acceptable scan times. As modern semiconductor packages become more complex, there are increasing demands for 3D X-ray instruments to image encapsulated structures and failures with high productivity and efficiency. With the challenge to precisely localize fault regions, it may require high-resolution imaging with a FOV of tens of millimeters. This may take over hundreds of hours of scans if many high-resolution but small-volume scans are performed and followed with the conventional 3D registration and stitches. In this work, a novel deep learning reconstruction method and workflow to address the issue of achieving highresolution imaging over a large FOV is reported. The AI powered technique and workflow can be used to restore the resolution over the large FOV scan with only a high-resolution and a large FOV scan. Additionally, the 3D registration and stitch workflow are automated to achieve the large FOV images with a recovered resolution comparable to the actual high-resolution scan.

3D X-ray tomography plays a critical role in electronic device failure analysis, but it can take several hours to overnight to get sufficient resolution in fault regions to detect and identify defects. In this paper, we propose a machine learning based reconstruction technique that can speed up data acquisition by a factor of four or more, while maintaining image quality. The method, which uses neural networks, extracts signals from low-dose data more efficiently than the conventional Feldkamp-Davis-Kress (FDK) approach, which is sensitive to noise and prone to aliasing errors. Several semiconductor packages and a commercial smartwatch battery module are analyzed using the new technique and the results compared with those obtained using conventional methods. The neural network can be trained on as little as one tomography image and the only requirement for the training data is that the sample or region of interest is well represented with all characteristic features in the field-of-view.

Lock-in thermography (LIT) has been successfully applied in different excitation and analysis modes including classical LIT, analysis of the time-resolved temperature response (TRTR) upon square wave excitation and TRTR analysis in combination with arbitrary waveform stimulation. The results obtained by both classical square wave- and arbitrary waveform stimulation showed excellent agreement. Phase and amplitudes values extracted by classical LIT analysis and by Fourier analysis of the time resolved temperature response also coincided, as expected from the underlying system theory. In addition to a conceptual test vehicle represented by a point-shaped thermal source, two semiconductor packages with actual defects were studied and the obtained results are presented herein. The benefit of multi-parametric imaging for identification of a defect’s lateral position in the presence of multiple hot spots was also demonstrated. For axial localization, the phase shift values have been extracted as a function of frequency [4]. For comparative validation, LIT analyses were conducted in both square wave and arbitrary waveform excitation using custom designed and sample-specific stimulation signals. In both cases result verification was performed employing X-ray, scanning electron microscopy (SEM) and energy dispersive x-ray (EDX) as complementary techniques.

Lock-in thermography (LIT) phase data is used to generate phase shift versus applied lock-in frequency plots to estimate defect depth in semiconductor packages. Typically, samples need to be tested for an extended time to ensure data consistency. Furthermore, determining the specific point on the thermal emission site to collect data from can be challenging, especially if it is large and dispersive. This paper describes how the use of new computational algorithms along with streamlined and automated workflows, such as self-adjusting thermal emission site positioning and phase measurement auto-stop, can result in improvements to data repeatability and accuracy as well as faster time to results. The new software is applied to generate the empirical phase shift versus applied lock-in frequency plot using 2.5D IC devices with known defect location. Subsequently, experimental phase shift data from reject 2.5D IC devices with unknown defect locations are obtained and compared against the empirical phase shift plot. The defect Z-depth of these devices are determined by comparing where the experimental phase shift data points lies with respect to empirical phase shift plot and validated with physical failure analysis (PFA).

Industry and market requirements keep imposing demands in terms of tighter transistor packing, die and component real estate management on the package, faster connections and expanding functionality. This has forced the semiconductor industry to look for novel packaging approaches to allow for 3D stacking of transistors (the so called “More than Moore”). This complex 3D geometry, with an abundance of opaque layers and interconnects, presents a great challenge for failure analysis (FA). Three-dimensional (3D) magnetic field imaging (MFI) has proven to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allows for submicron vertical resolution. 3D X-ray microscopy (XRM) enables 3D tomographic imaging of advanced IC packages without the need to destroy the device. This is because it employs both geometric and optical image magnifications to achieve high spatial resolution. In this paper, we propose a fully nondestructive, 3D-capable workflow for FA comprising 3D MFI and 3D XRM. We present an application of this novel workflow to 3D defect localization in a complex 2.5D device combining high bandwidth memory (HBM) devices and an application specific integrated circuit (ASIC) unit on a Si interposer with a signal pin electrical short failure.

Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel nondestructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper, we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.