This paper demonstrates that e-beam assisted device alteration (EADA) is a powerful, high-resolution technique for fault isolation debug for advanced technology nodes. A case study using this technique is reviewed and shows successful isolation of a defective single inverter. In addition, fundamental studies of ring oscillator behavior and device perturbations with e-beam exposure found clear correlations for electron beam exposure with NMOS/PMOS device parameters. Electron-hole pair generation in the device with beam exposure is likely the main component for the perturbation, but there may be other contributing factors including charging effects and/or heating.

For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.

The examination of partially deprocessed ICs for well imaging has been investigated. First it has been shown [1] that Ga+ FIB imaging can readily and strongly highlight the N-well / P-well boundary in an IC as shown again here. Second, a model which only considers secondary electron creation and scattering [2] is confirmed to be sufficient for understanding these imaging effects. Heavy Ga doping provides no marked change in PVC (passive voltage contrast). Then comparisons in the same field of view between optimized He+ and Ga+ imaging, has shown that He+ provides much greater PVC contrast when looking through deep oxide, and much better resolution on shallow surfaces. The quantitative model Stopping and Range of Ions in Matter (SRIM) [3] was consulted and confirmed these expectations for resolution and depth superiority of the He+ beam. According to the SRIM, there may even be less damage from the He+ beam. Yet these known effects of Ga+ damage has not prevented its widespread use in semiconductor FA and process monitoring. Thus, the use of GFIS (Gas field ion source) He+ beam for voltage contrast and junction imaging warrants further exploration.

Laser scanning microscope (LSM) based waveform acquisition is widely used in advanced CMOS IC design validation and debug application. Complex waveforms obtained from LSM probing on CMOS ICs are often difficult to fully comprehend without deep understanding of the complex physics involved even in planar CMOS. The introduction of 3-D Tri-Gate transistors since 2010 made this even more challenging. In this paper, we present both model based simulation and probing validations on the most advanced 3D Tri-Gate based CMOS ICs that give us a clear understanding of the nature of these complex waveforms.

Logic State Imaging (LSI) using Infra-Red Emission Microscopy (IREM) [1-4] has been an indispensable technology for silicon CMOS process development and product debug applications. Its main limitations are relatively poor spatial resolution due to the broadband near-infrared photons emitted, and poor Signal to Noise Ratio (SNR) with low voltage and low leakage processes and products. Continuous-Wave Laser Scanning Microscope (CW-LSM) based Signal Imaging and Probing (CW-SIP) [5-9] technology is also widely used. It features inherently better spatial resolution than IREM, due to the use of monochromatic 1319nm or 1064nm laser light, and high SNR due to its weaker dependence on voltage and leakage, and, for signal imaging applications, the use of narrow band detection to reduce noise. However, CW-SIP can only detect modulating signals, so it couldn’t previously be applied to LSI. In this paper, we introduce an innovative approach that overcomes this limitation to enable Laser Logic State Imaging (LLSI). Actual fault isolation and design debug cases using this technology are presented to show its advantages in terms of resolution (>50% better), SNR (>2X better) and throughput time improvement, especially at low voltages (down to 500mV).

A novel method for obtaining diffraction limited high resolution images, and increased signal to noise ratio (SnR), for imaging and probing silicon based complementary metal oxide semiconductor field effect transistor (CMOS, and MOSFET) integrated circuits (IC), is presented. The improved imaging is based on the sub wavelength features’ asymmetric layout, which is dictated by the lithography design rules constrain in CMOS IC and their interactions with polarized light. This asymmetry in layout and the inherent stress engineering on the CMOS IC, produce both dichroism and birefringence in silicon (Si). An elegant design enabled us to obtain two images with orthogonal polarization detection to take advantages of the dichroism and birefringence in Si based CMOS IC. Differential Polarization Image (DPI) is obtained by subtracting the two orthogonal polarization resolved images. On infrared emission microscopes (IREM), DPI in optical imaging mode and DPI plus probing [DPIP] in emission mode, showed 2X or more in terms of optical resolution (imaging mode) and 2X or more SnR (emission-probing mode) improvements. Striking images in probing mode, revealing previously “invisible” emission, were demonstrated.

As device dimensions continue to shrink, process defects tend to become more subtle. For most failure analysis (FA) studies, it is important to identify the defect location for the subsequent material analysis. To achieve this, nano-probing has been widely used in the FA community. Copper (Cu) contacts posed a significant challenge to nano-probing since Cu is soft and tends to deform during measurements. In addition, Cu oxidizes quickly in air, increasing contact resistance significantly between the probes and devices. This paper introduces electroless cobalt (Co) plating on Cu contacts for nano-probing to overcome these technical problems. As Cu is soft and oxidized quickly in air, the technique presented in this paper provides a technical solution for nano-probing on Cu contacts. With carefully characterized Co plating time, this technique can be used not only on Cu contacts but also on Cu interconnection.

In this paper, we report on the first observation and study of two-photon absorption (TPA) based laser assisted device alteration (LADA) using a continuous-wave (CW) 1340nm laser. The study was conducted using LADA systems equipped with high numerical aperture (NA) liquid and solid immersion lens objectives on Intel’s 45 nm and 32 nm multiprocessor units (MPU) and test chips. The power densities achievable using these lenses are similar to those reported in the literature for TPA in silicon of CW 1455nm light [1]. We show that the induced photocurrent has a quadratic dependence on the input laser power, a key indicator of two-photon phenomenon. Our results imply that even when using 1340nm wavelength CW lasers, there is a potential for laser invasiveness with the high power densities achievable using high NA objectives. Laser induced damage of the DUT is also a possibility at these high power densities, particularly with the solid immersion lens (SIL). However, we show that the DUT damage threshold can be increased by reducing the DUT’s temperature. Finally, we present results demonstrating a >40% improvement in localization of critical timing faults using TPA based LADA, when compared to traditional 1064nm wavelength (single-photon absorption) LADA.