Mechanical sample preparation is a crucial and indispensable step in modern failure analysis (FA). Traditional methods excel in reducing bulk silicon to thicknesses of several tens of micrometers. However, contemporary demands necessitate sample preparation below 10 µm or even below 5 µm, which is challenging, time-consuming, and requires an expensive toolset and advanced operator expertise. Existing methods, which rely on mechanical components for bulk removal, induce mechanical stress and microcracks that can alter the electrical characteristics of the sample. Maintaining the sample's electrical behavior is essential for accurate FA. This paper introduces a novel approach to sample preparation that employs concepts from wafer-level chemical mechanical polishing (CMP). This method ensures reliable sample preparation without introducing microcracks, accurately halts material removal at the shallow trench isolation (STI) – or deep STI - level, and maintains the sample's electrical functionality. The proposed approach is discussed in detail, including successful thinning of various sample types to the STI level, which were subsequently tested for electrical functionality.

When aiming for extreme thinning of the bulk silicon down to the shallow trench isolation (STI) level, endpoint determination is a challenging task. Here, we present a novel approach providing reliable access to the STI level of single dies. Therefore, we transfer the wafer-based CMP process to be applicable to single dies on a table-top machine. In a first step, the developed process is applied to the whole IC backside simultaneously. Using a highly selective slurry with a material removal ratio from Si to SiO of more than 500:1 ensures that the STI level remains intact. Two types of samples have been prepared for experiments performed for this paper. A 115mm x 80mm flip-chip bonded device with a bulk silicon thickness of 500μm has been prepared to STI level within less than 4 hours.