With the rapid development of semiconductor manufacturing technologies, IC devices evolve to smaller feature sizes and higher densities, and thus the task of performing successful failure analysis (FA) is becoming increasingly difficult. Device miniaturization often requires high spatial resolution fault isolation and physical analysis [1]. To cater to the shrinking of devices, extensive process improvements have been conducted at the front-end-of-line (FEOL) structures. As a result, among the numerous types of defects leading to chip failure, FEOL defects are becoming more common for devices of advanced tech nodes [2]. Therefore, it becomes more complexity and difficulty on searching the physical defect. Sample preparation is a key activity in material and failure analysis. In order to image small structures or defects it is often necessary to remove excess material or layers hiding the feature of interest. Removing selected layers to isolate a structure is called delayering. It can be accomplished by chemical etching using liquid or plasma chemistry, or by mechanical means, by polishing off each unwanted layer.

In this paper, a zero yield case relating to a systematic defect in N+ poly/N-well varactor (voltage controlled capacitor) on the RF analog circuitry will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging and nano-probing, manual layout path tracing, FIB circuit edit, selective etching together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical for a foundry company with restricted access to data on test condition setup to duplicate the exact failure as well as no layout tracing available at time of analysis. The systematic defect was due to gate oxide breakdown as a result of implanter charging. It serves as a good reference to other wafer Fabs encountering such an issue.

Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.

In this paper, a low yield case relating to a systematic array of failures in a ring pattern due to ADC_PLL failures on low yielding wafers will be studied. A systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current imaging, layout path tracing, PVC and XTEM together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical in a wafer foundry in which there is minimal available data on the test condition setup to duplicate the exact failure. The ring pattern was due to systematically open via as a result of polymer built-up from plasma de-chuck issue. It would serve as a good reference for a wafer Fab that encounters such an issue.

Wire bonding continues to remain as the dominant chip interconnect technology in the far backend process, regardless of the shrinkage of microchip Al bond pad size and the increase in the number of I/O connections in the modern ICs. The reliability of IC devices is directly affected by the quality of adhesion between wire bond and microchip Al pad. Many factors, such as the wafer fab process residue and corrosion, creep-induced wire breakage and electrostatic damage, may result in poor adhesion. In this paper, we show a p-channel Field-Effect Transistor (pFET) failure caused by a mismatch in the bond pad size and the wire bond diameter as well as electrostatic damage during wire bonding. The failure analysis results, failure mechanism and the design rule of microchip Al bond pad in wafer fabrication are discussed. FA investigations were performed on the high gate leakage (nA to mA level) issue in the packaged pFET. It was found that two major factors contributed to the failure, namely mechanical and electrostatic damage. The mechanical damage was mainly due to incompatible Al pad size and bond wire diameter. More specifically, in the failed device, the bond wire diameter was larger than half size of the bond pad opening, contrary to the general design rules of wire bonding. The failure to adhere to the design rule resulted in the device failure. In addition, the electrostatic damage during wire bonding resulted in defects of poly Si/gate oxide and thus the high gate leakage. In this paper, the FA results, failure mechanism of the high gate leakage and the bond pad design rule will be discussed. Also, it will be demonstrated that to achieve good bonding quality and eliminate mechanical and ESD damage the diameter of the bond wire should be equal to or smaller than half of the bond pad opening.