Power devices are now ubiquitous and integral in control of systems across various sectors of the economy. Silicon-based power devices still dominate in most of the applications although new materials and device architectures are becoming common in the next generation of devices. While several techniques to characterize the overall device properties are necessary, the fundamentals in several of these power devices such as Insulated Gate Bipolar Transistors (IGBTs) still rely on healthy junctions for optimal device performance. The technique of Electron Beam Induced Current (EBIC) is used to examine the depletion zones of the p/n junctions between drift and body regions of the device. Simple sample preparation methods such as cleaving the device allows quick cross-section evaluation of the device structure and electrical characterization using EBIC yields good data. The role of acceleration potential on depletion zone thickness is considered during the analysis of intact die and cross-sections. While low voltage EBIC provides images of the p/n junctions in cross-sections, it is found that high voltage (30 kV) EBIC images can also be used to image these same p/n junctions and therefore may point to a very quick line monitor or means for early failure analysis of these devices.

Microscopic imaging and characterization of semiconductor devices and material properties often begin with a sample preparation step. A variety of sample preparation methods such as mechanical lapping and broad ion beam (BIB) milling have been widely used in physical failure analysis (FPA) workflows, allowing internal defects to be analyzed with high-resolution scanning electron microscopy (SEM). However, these traditional methods become less effective for more complicated semiconductor devices, because the cross-sectioning accuracy and reliability do not satisfy the need to inspect nanometer scale structures. Recent trends on multi-chip stacking and heterogenous integration exacerbate the ineffectiveness. Additionally, the surface prepared by these methods are not sufficient for high-resolution imaging, often resulting in distorted sample information. In this work, we report a novel correlative workflow to improve the cross-sectioning accuracy and generate distortion-free surface for SEM analysis. Several semiconductor samples were imaged with 3D X-ray microscopy (XRM) in a non-destructive manner, yielding volumetric data for users to visualize and navigate at submicron accuracy in three dimensions. With the XRM data to serve as 3D maps of true package structures, the possibility to miss or destroy the fault regions is largely eliminated in PFA workflows. In addition to the correlative workflow, we will also demonstrate a proprietary micromachining process which is capable of preparing deformation-free surfaces for SEM analysis.