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1-4 of 4
Andrew Erickson
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Proceedings Papers
Plasma FIB DualBeam Delayering for Atomic Force NanoProbing of 14 nm FinFET Devices in an SRAM Array
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 388-400, November 1–5, 2015,
Abstract
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The result of applying normal xenon ion beam milling combined with patented DX chemistry to delayer state-of-theart commercial-grade 14nm finFETs has been demonstrated in a Helios Plasma FIB DualBeam™. AFM, Conductive-AFM and nano-probing with the Hyperion Atomic Force nanoProber™ were used to confirm the capability of the Helios PFIB DualBeam to delayer samples from metal-6 down to metal-0/local interconnect layer and in under two hours produce a sample that is compatible with the fault isolation, redetection, and characterization capabilities of the AFP. IV (current-voltage) curves were obtained from representative metal-0 contacts exposed by the PFIB+DX delayering process and no degradation to device parameters was uncovered in the experiments that were run. Compared to mechanically delayering samples, the many benefits of using the PFIB+DX process to delayer samples for nano-probing were conclusively demonstrated. Such benefits, include sitespecificity, precise control over the amount of material removed, >100μm square DUT (device under test) area, nm-scale flatness over the DUT area, nm-scale topography between contacts and the surrounding ILD, uniform conductivity across the DUT area, all with no obvious detrimental effects on typical DC device parameters measured by nano-probing.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 204-208, November 2–6, 2008,
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MOSFET devices are routinely measured at the probe pad level with conventional capacitance-voltage (CV) measurement instruments. Such measurements are done at the front end of line (FEOL) and back end of line (BEOL) process completion levels. The CV data is used to monitor the process and verify certain parametrics such as effective oxide thickness (EOT), Tox, gate drain overlap capacitance (Miller capacitance), trapped charge, diffusion/halo implant oxide leakage, doping concentration, threshold implant level and many others. This type of testing is treated at length in the classic text of Nichollian and Brews [1]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) of discrete MOSFET devices and the method of performing scanning capacitance imaging (SCM) have been previously presented [2]. In that work, the authors used a capacitance sensor to measure the capacitance of an individual failing embedded DRAM capacitor. This paper will describe nanoprobe CV measurements of a discrete finger device from a multiple finger test structure and show comparable results obtained at the probe pad level, using an improved version of the earlier capacitance sensor. By comparing the BEOL test structure measurements with NCVS results from a single finger, we will verify and calibrate the nanoprobing technique.
Proceedings Papers
ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 46-51, November 4–8, 2007,
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Nanoprobing logic based SOI embedded DRAM cells for on-processor designs poses different challenges than probing conventional six transistor SRAM designs. This paper will describe nanoprobing logic based embedded DRAM (eDRAM) cells in 65nm SOI applications. We will also describe probe placement and measurement methodology for electrical characterization of leakage between deep trench capacitors composing those eDRAM designs. The introduction of nano CV metrology and scanning capacitance imaging for use in characterizing DRAM capacitors will also be discussed.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 497-502, November 12–16, 2006,
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To reconstruct discrete device threshold characteristics at tungsten contact level with atomic force probe (AFP), specific care in making drive current measurements is essential. Kelvin probing as well as the proper placement of the AFP probes themselves is an absolute requirement for insuring precise measurements. For this paper, NFET and PFET test structures employing 3 micrometer gate widths are used to simulate a sense-amp device. The results obtained using normal pad-level probing on a conventional probe station with results from an AFP nanoprober with and without Kelvin sensing are compared. These measurements are also compared with the nominal or expected design rule values. Experimental results comparing AFP Kelvin measurements at contact level on the same MOSFET test structure versus measurement obtained conventionally at pad level underscores the importance and value of AFP Kelvin measurements.