Competitive circuit analysis of an Integrated Circuit (IC) is one of the most challenging types of analysis. It involves various high technology steps of IC die de-processing/de-layering; keeping precise planarity from metal layer to metal layer, Scanning Electron Microscope (SEM) imaging and images mosaicking, image recognition and Graphic Database System (GDS) segmentation processes and finally logic and architecture level analysis. One of the most complicated analysis is Power Management and Power Distribution [2] on the entire IC die when no datasheet or other IC’s information is available. Power Distribution analysis requires the highest level of architecture analysis, not feasible by conventional Reverse Engineering (RE) methods or extremely costly. The current paper discusses and demonstrates a new inventive methodology of Power Distribution analysis using known FIB Passive Voltage Contrast (PVC) effects [1]. This patented technique provides significant time and resources saving.

Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.

Secondary electron signal is widely used in Focused Ion Beam (FIB) systems for imaging and endpointing. In the application of integrated circuit modification, technology has progressed towards smaller dimensions and higher aspect ratios. Therefore, FIB based circuit modification processes require the use of primary ion beam currents below 10 pA and Gas Assisted Etching (GAE). At low beam currents, short pixel dwell times and high aspect ratios, the level of available secondary electrons for detection has declined significantly. FIB GAE and deposition requires delivery and release of a gaseous agent near the beam scanning area, and involves insertion of a gas delivery nozzle made of conductive material and grounded for charge prevention purposes. The proximity of a grounded gas delivery nozzle to the area being milled and/or imaged creates a “shielding” effect, further lowering secondary electron signal level. The application of a small positive bias to the gas delivery nozzle provides an effective way of reducing the “shielding” effect. Depending on the geometrical arrangement of the gas delivery system and other conductive objects in the chamber, an optimized nozzle bias potential can create conditions favorable for enhanced extraction and collection of secondary electrons. The level of the secondary electron image signal, collected in an FEI Vectra 986+ system, from a grounded copper sample with the nozzle extended and biased can be enhanced as much as six times as compared to the grounded nozzle. Secondary electron intensity endpoint is improved on backside samples, however shielding of the nozzle field by the bulk silicon substrate limits the electron extraction effect from within a via. For front side edits the improvement of endpoint signal level can be dramatic. Lateral image offset induced by the electrostatic field of a biased nozzle, can be removed by software position compensation.

Advances in FIB (focused ion beam) chemical processes and in the Ga (gallium) beam profile are discussed; these advances are necessary for the successful failure analysis, circuit edit and design verification of advanced, sub-0.13µm Cu devices. Included in this article are: a novel FIB method (CopperRx) for smoothly milling thick, large grained Cu lines; H2O and O2 processes for cleanly cutting thin, smaller grained Cu lines, thereby forming electrically open interconnects; a XeF2 GAE (gas assisted etching) process for etching low k, CVD dielectrics such as F and C doped SiO2; H2O and XeF2 GAE processes for etching low k, spin-on, organic dielectrics such as SiLK; a recently developed recipe for the deposition of SiO2 based material with intermediate resistivity (10 6 µohm·cm) which is useful in the design verification of frequency sensitive, high speed analog and SOC (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling.