Circuit edit (CE) workflows are well established for FIB energies of 30kV and above. The small spot size associated with such energies provides good milling acuity and imaging resolution needed for advanced CE applications. However, with the introduction of FinFET transistors and decreasing technology nodes, the dramatic reduction in STI to gate distance reduction poses some challenges to circuit editing at these high energies. These include transistor performance degradation due to Ga+ implantation as well as significant lateral scattering beyond the Node Access Hole (NAH) as defined by the pattern. In addition, the relatively fast milling speeds may not give enough control to the user to endpoint at the appropriate layer. In this paper, a group of FinFET transistors on a special test chip was edited with the Ga beam at different energies. Transistor performances were then characterized to evaluate any degradation. The resulting characterization revealed how the transistor performance was affected by the injected ion beams and provided a guideline for the low-kV circuit edit workflow. A novel low-kV FIB workflow was proposed to minimize the transistor damage and maintain the IC functionality after the CE process. The workflow was applied to a challenging CE problem on a 5nm FinFET device. This task included step by step backside delayering at 5kV, preparing the sample for the final circuit edit operation at Metal-1. Working at low landing energies (e.g. 5kV) lowers subsurface damage and reduces etching speed, but with trade offs including lower image resolution, milling acuity, sputtering yield and signal to noise ratio (SNR). However, the consequences of these effects can be mitigated by use of appropriate chemistries with closed loop delivery control and extremely low beam currents (≤1pA), in concert with double aperture beam shaping to minimize beam tails. On the 5nm FinFET device, we demonstrate good delayering control by optimization of beam currents, and gas delivery on the Centrios HX circuit edit system from Thermo Scientific.

Focused ion beam (FIB) systems use a gallium liquid metal ion source as the source of the ions, providing a typical beam current range of 1 pA to 20-60 nA. Using a reactive gas in addition to the FIB usually enhances the etch rate from 1 to 15 times, but with the combination of xenon difluoride gas and a silicon substrate the enhancement can be over 1000 times. Such an enhancement makes the removal of large volumes of Si more practical, even with the typical upper end of FIB currents of 20-60 nA. This paper discusses the application of full-thickness silicon trenching to the process development of WtW bonding. With the increase in 3DIC, it is expected that fresh process characterization and failure analysis techniques will be required. The work presented shows the feasibility of extending FIB techniques to the process development of wafer-to-wafer bonded samples even on full-thickness wafers.