Photon Emission Microscopy is the most widely used mainstream defect isolation technique in failure analysis labs. It is easy to perform and has a fast turnaround time for results. However, interpreting a photon emission micrograph to postulate the suspected defect site accurately is challenging when there are multiple abnormal hotspots and driving nets involved. This is commonly encountered in dynamic emission micrographs that are caused by open defects in digital logic. This paper presents a methodology incorporating layout-aware trace analysis and post schematic extraction with test bench analysis to enhance the diagnostic resolution on the suspected defective net(s).

Most modern system on-chip incorporates a significant amount of embedded memories to achieve a reduced power consumption, higher speed and lower cost. In general, such memories are evaluated using built-in self-testing methods and in the event of a failure, bitmapping is heavily relied on for fault localization to guide subsequent failure analysis. However, a fast yield ramp can be impeded when bitmapping is not enabled in time or is inaccurate. This work studies the feasibility of employing electrically-enhanced LADA as an alternative method to debug embedded memory failures. Results are presented to demonstrate that the resolution of localization depends on the precision of diagnostic test pattern used and the laser spot size.

EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.

Unlike photon emission microscopy which is usually the first go-to technique in tester-based or dynamic electrical fault localization, infrared thermal microscopy does not play a similar routine role despite its comparable ease in application. While thermal emission lacks in optical resolution, we demonstrate superior sensitivity and accuracy over photon emission on dynamic fault localization of backend-of-line short defects.