In this paper, we present a technique for device temperature measurement using spontaneous near infrared (NIR) emission from an Integrated Circuit (IC). By leveraging modeling and data analysis, time-integrated emission measurements are used to estimate the temperature increase due to switching activity inside the channel of CMOS transistors. The non-invasive nature of the technique allows one to reliably monitor the temperature of any device on-chip without the need for circuit modifications or dedicated on-chip sensors and with a higher spatial resolution than thermal cameras. This method has important applications for modeling heat dissipation during early process development, localizing hot spots, calibrating on-chip sensors, etc. In this paper, temperature is estimated by fitting empirical emission data to an emission model that can be solved for device channel temperature.

In this paper, we present the latest results obtained with a 2D Picosecond Imaging Circuit Analysis (PICA) camera with enhanced Near InfraRed (NIR) sensitivity [1] for taking 2D Time Resolved Emission (TRE). We will discuss key applications where the time-resolved imaging capability is very effective in reducing the debug time and improving the interpretation of the failure signatures of several VLSI chips. Besides conventional chip diagnostics, specific focus will be dedicated to new areas of applications, such as security and reverse engineering [2]. We will also discuss spectral analysis and other techniques that can be used to extract valuable information from the PICA dataset.

In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.

We describe a test chip designed and fabricated in 32nm CMOS SOI. The test chip was developed to assist in the characterization and testing of hot electron emission based test systems for both existing and forthcoming technology nodes, and contains circuit structures of increasing density and complexity. We also describe some unique circuit functions that may be of use in other applications

In this paper, we discuss the use of a tester-based methodology to enhance the spatial resolvability and interpretation of time-integrated and time-resolved emission measurements. This technique, first presented at [1] for chip diagnostics and failure localization, is very powerful for extending the capability of modern analytical tools beyond the limits of existing optics and detectors. In particular, we will discuss how the proposed method works and present several test cases for both static and dynamic emission measurements that allow signals from gates 150 nm apart to be resolved.

In this paper, near-infrared photon emission spectroscopy measurements from ring oscillators in 45 nm and 32 nm SOI process technology are compared. Employing a cryogenically cooled camera, the measurements cover a broad spectral range from 1200-2200 nm. Both leakage and switching emission, increase monotonically with the wavelength, suggesting measurements should be made at longer wavelengths than has historically been practiced. The paper discusses the optimum cut-off wavelength for maximum signal-to-noise ratio and the obvious importance of reduced ambient temperature for performing measurements.

In this paper, we evaluate a novel, position-sensitive, singlephoton detector with enhanced Near InfraRed (NIR) sensitivity [1-3] for taking 2D Time Resolved Emission (TRE), also known as Picosecond Imaging for Circuit Analysis (PICA), in future low voltage SOI technologies. In particular, we will investigate and quantify the sensitivity of two generations (Gen. I and Gen. II) of PICA cameras by Hamamatsu Photonics as a function of the power supply voltage on an IBM 45 nm SOI test chip. Additionally, we will compare the results to the performance obtained with an InGaAs Single Photon Avalanche Diode (SPAD) from DCG Systems [4]. Finally we will show a case study and an advanced analysis and localization technique that takes advantage of the 2D capability of the camera.

Light Emission due to Off-State Leakage Current (LEOSLC) is used in combination with the Picosecond Imaging Circuit Analysis (PICA) method to effectively diagnose and localize defects in a broken scan chain. As usual, the emission base method shows to be very effective in debugging the problem; the defect is successfully identified by the optical technique and confirmed by Physical Failure Analysis (PFA).

In this paper we discuss the use of Emission Microscopy (EMMI) to examine the events leading to latchup for various Input/Output (I/O) pins of a test chip in order to study the factors that impact latchup sensitivity of VLSI chips. The goal of our study is to identify and characterize the structures that are most prone to latchup in test chips, thus providing countermeasures to be used to improve the overall latchup resistance of commercial chips. As it has been shown in literature [1-3], EMMI can be used to localize areas that are latching up. Here we focus our attention on electrostatic discharge (ESD) into I/O pins, which may lead to latchup inside I/O circuits or in their proximity.

In this paper we examine the use of the Superconducting Single-Photon Detector (SSPD) [1] for extracting electrical waveforms on an IBM microprocessor fabricated in a 0.13µm technology with 1.2V nominal supply voltage. Although the detector used in our experiments is prototype version of the one discussed in [1] demonstrating lower performance, we will show that it provides a significant reduction in acquisition time for the collection of optical waveforms, thus maintaining the usability of the PICA technique for present and future low voltage technologies.