Silicon photonics has emerged as a key solution for on-chip communication to improve computational systems especially for AI workloads. Testing of such photonic integrated circuits (PICs) is key to deliver known good dies to be co-packaged with the compute IC. The recent availability of commercial photonic testers has allowed for monitoring most optical components at wafer level using vertical grating couplers. However, the measurement of optical insertion loss prior to fiber attach of edge-coupled spot size converters remains one of the significant challenges. In this article we demonstrate the use of a novel system for wafer–level optical edge-coupling insertion loss measurement. This method proved to be effective in capturing manufacturing process issues impacting insertion loss with a relatively fast turnaround time compared to fiber attach.

Physical Failure Analysis (PFA) is essential for SRAM yield learning, especially in new technologies or FAB transfers. For this to be successful, physical coordinates for tested bitcell failures must be accurately calculated and verified. The timeline for this process can vary dramatically based on the extent and complexity of any issues. This paper details the successful use of fault localization on isolated, voltage sensitive failures to achieve confidence in verification of physical location prior to PFA.

With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.