Skip Nav Destination
Close Modal
Update search
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
NARROW
Format
Subjects
Article Type
Volume Subject Area
Date
Availability
1-2 of 2
A.G. Street
Close
Follow your search
Access your saved searches in your account
Would you like to receive an alert when new items match your search?
Sort by
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 22-25, October 28–November 1, 2018,
Abstract
View Papertitled, Correlation of Thermal Rise Time to Sample Depth in Multi-Die Stacked Devices
View
PDF
for content titled, Correlation of Thermal Rise Time to Sample Depth in Multi-Die Stacked Devices
Dynamic Digital Modulation, an adaptation of Lock-In Thermography, has been shown to be a useful technique to establish the relative Z-depth of thermal sources in integrated circuits. In order to determine the specific depth of a thermal source it is necessary to correlate known depths to measured thermal rise time. In this work, multi-die stacked memory devices are used as calibration sources to correlate a thermal source at individual die to the measured thermal rise time.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 27-32, November 15–19, 2009,
Abstract
View Papertitled, Subsurface Imaging of Multi-Level Integrated Circuits Using Scanning Electron Acoustic Microscopy
View
PDF
for content titled, Subsurface Imaging of Multi-Level Integrated Circuits Using Scanning Electron Acoustic Microscopy
The capability of the Scanning Electron Acoustic Microscopy (SEAM) technique for high resolution non-destructive subsurface imaging at different depths for a multi-level integrated circuit is assessed. Experimental results using a beveled DRAM IC sample are used to quantify the effect of the electron beam energy and modulation frequency on contrast, spatial resolution and depth of focus of SEAM amplitude and phase images.