Customer-reported device failures that cannot be replicated during incoming retests present a significant challenge in semiconductor testing. These discrepancies often arise because customer applications subject devices to more extensive and prolonged stress conditions than standard final testing procedures allow. This paper presents a novel method for detecting subtle marginalities in main logic failures by modifying launch and capture pulses in transition delay patterns. Our approach enhances failure detection capabilities in failure analysis environments, particularly for marginal failures that initially pass automated test equipment (ATE) retesting despite customer-reported issues. We demonstrate the effectiveness of this technique through a case study where we successfully reproduced a customer-observed failure by adjusting the timing parameters. This method bridges the gap between standard test conditions and real-world application environments, enabling more accurate fault detection and validation.

Laser voltage imaging techniques are widely used in failure analysis for detecting defects in digital circuitry. In case of scan chain failures that are substantially static, this is really the most suitable application. In this paper we explore and demonstrate the potential of this method for characterizing transition delay failures in combinatorial logic, through the real-time measurement of the behaviour of each transistor in the cell.

The aim of this work is to disclose about the difficulties of handling quasi-static transition failures and propose one possible strategy to detect and locate them in a failure analysis test environment with the most appropriate fault localization technique.

Analog fault localization for functional failures is usually a very complex task, especially because a deep knowledge of all the functionalities of the device is often required. In addition, when the part is analyzed in application conditions, the interpretation of the anomalous emissions in the failed part and its link to the failing elementary component is not so obvious. The adoption of the analog quiescent current (IDDa) allows to address directly the failing elementary component inside the suspected block.