This presentation provides an overview of nanoprobe systems and what they reveal about defects and abnormalities in semiconductor device structures and materials. The presentation covers the basic operating principles, implementation, and capabilities of atomic force probe and beam-based imaging techniques, including AFP pico-current contrast and scanning capacitance imaging, SEM/FIB active voltage contrast imaging, and SEM/FIB electron-beam absorbed current (EBAC), induced current (EBIC), and induced resistance change (EBIRCH) imaging. It also includes guidelines for probing transistors and copper metallization and case studies in which nanoprobing was used to analyze gate oxide and substrate defects, intermittent bit cell failures, threshold voltage shifts, and time-domain popcorn noise.

This presentation covers the basic physics needed to understand and to effectively apply backside IC analysis techniques to flip-chip packaged die. It describes the principles of light transmission through silicon and the factors that influence optical image formation from the backside of the wafer or die. It also provides information on the tools and techniques used to expose surfaces, regions, and features of interest for analysis. It describes the steps involved in CNC milling, mechanical grinding and polishing, reactive ion etching (RIE), laser microchemical (LMC) etching, and milling and etching by focused ion beam (FIB). It explains where and how each technique is used and quantifies the capabilities of different combinations of methods.

This presentation introduces the practice of focused ion beam (FIB) chip editing and its power and versatility as a problem-solving tool. It begins with a review of the features and functions of FIB systems, the role of gas chemistry in milling, etching, and deposition, and the use of IR imaging for navigation and targeting. It goes on to identify challenges due to packaging materials, chip-package interactions, and other factors, and in each case, provide alternate approaches and procedures to circumvent potential problems. It also covers advanced practices and methods and assesses potential future advancements.

This presentation covers ion beam analytical tools, their capabilities, and uses. It provides an overview of ion sources, examines emerging trends in surface analysis, and assesses the potential of ultrafast lasers for panoscopic patterning, athermal ablation, and elemental analysis. It compares and contrasts liquid metal, gas field, and plasma sources and presents examples highlighting the capabilities of FIB-SIMS and FIB-SEM Auger/XPS surface analysis techniques. It also introduces computationally guided microspectroscopy (CGM) and assesses its potential impact on multi-variant analysis, point spread deconvolution, and compressed sensing.

This paper provides an overview of the semiconductor analysis process at BMW. It explains how it was developed and how it differs from the failure analysis process used in semiconductor fabs. It describes the general process flow from first analyses through descending levels of localization at different length scales. It discusses sample preparation procedures, test methods and equipment, and advanced techniques. In the work presented here, the authors explain how they combined ToF-SIMS with STEM lamella preparation in a FIB-SEM, which allowed them to correlate concentration variances in an underlying layer with surface anomalies discovered during light microscope inspection.

The characterization of back side illumination (BSI) image sensors is challenging because of the unique construction of such sensors with silicon on top. A novel method for BSI image sensor characterization is presented in this paper. The proposed approach is based on backside circuit editing using ion beam and optical imaging techniques. This provides access to buried conductors and creates probe points for measurements that can be made using an optical, electron beam, or mechanical micro/nano prober.

The automation of TEM imaging and lamella preparation using focused ion beam (FIB) technology has gained significant momentum, particularly in the development of microprocessors. A key requirement of automating TEM sample preparation is ensuring consistent thickness control and accurate targeting of features of interest in the ultra-thin lamella. This work examines the factors that impact both metrics. It explains how FIB pattern calibration requires milling to be divided into steps to minimize the effects of drift, how the height of the protective cap on the ion-beam tip influences sample thickness, and how FIB aperture erosion has little impact on lamella thickness until it reaches a certain point where the lamella profile cannot be reliably maintained. It was also found that the tail of the ion beam remains invariant during aperture degradation in the operable range and that it plays a prominent role in determining the cross-sectional thickness of the TEM lamella.

This paper evaluates the use of plasma etching for preparing TEM specimens to analyze high aspect ratio 3D NAND integrated circuits. By controlling plasma etching parameters, a relatively high material removal rate could be obtained. Moreover, through the control of etch time, the top region of the test specimens could be completely removed down through the expected number of layers, making it possible to resolve details throughout the entire sample, particularly in the middle region of the 3D NAND, using TEM cross-section analysis.

This paper evaluates the use of nanomilling and STEM imaging to analyze failure mechanisms in sub-50 nm InP HEMTS. The devices were life tested at elevated temperatures and biases and their electrical characteristics were measured at each stress interval. Devices that were damaged were investigated further to assess the underlying failure mechanism. Advanced microscopy with sub-nm resolution was employed to examine the physical characteristics of the failed HEMT devices at the atomic scale. As the paper explains, the examination was conducted using a focused ion beam/scanning electron microscope (FIB/SEM), an Ar gas ion nanomill, and STEM imaging.

This paper explains how to localize metal-to-metal short failures in DRAM using mechanical grinding, plasma FIB delayering, and electron beam induced resistance change (EBIRCH) analysis. Experiments show that the slope created during grinding is compensated by PFIB delayering, producing a high-quality planar surface in the target layer and site. Target layers can thus be prepared at any location (site-free), likewise, defective areas can be delayered to any depth without damage (layer-free). After delayering, exposed surfaces are generally flat enough to allow an electron beam to evenly penetrate the device for precise EBIRCH analysis. With the use of more advanced device preparation methods, EBIRCH analysis has a higher chance of successfully localizing metal line/via shorts even in large regions that include the aluminum layer.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

Convention hand polishing, which is widely used for delayering, is becoming increasingly difficult as metal lines and stacks in semiconductor devices get thinner. For one thing, endpointing at the exact targeted layer and region of interest is a major challenge. The presence of cobalt and its propensity to oxidize, thus complicating electrical measurements, is another challenge. In this study, the authors demonstrate an alternative delayering method based on plasma focused ion beam (PFIB) milling aided by DX gas. The workflow associated with the new method is more efficient than that of conventional hand polishing and can help prevent cobalt oxidation.

This paper describes a procedure for preparing packaged GaN devices for photon emission microscopy from the backside, which has proven to be an effective method for isolating faults. The deprocessing technique was developed for GaN devices formed on thick p ++ silicon substrates mounted in quad-flat no-lead (QFN) packages connected by gold wires. It consists of mechanical polishing, which removes backside metal and packaging material, and selective etching, which quickly etches the silicon while leaving the gold wires intact for electrical measurements. The authors describe each step of the process in detail and explain how emission spots are marked with a UV laser and analyzed in a FIB-SEM system to determine the underlying cause of failure.

This paper presents a large-volume workflow for fast failure analysis of microelectronic devices. The workflow incorporates a stand-alone ps-laser ablation tool and a FIB-SEM system. As implemented, the picosecond laser is used to quickly remove large volumes of bulk material while the Xe plasma FIB provides precise end-pointing to the feature of interest and fine surface polishing after laser ablation. The paper presents several application examples, including a full workflow to prepare artefact-free, delamination-free cross-sections in an AMOLED mobile display and the preparation of devices and packages (including flip chips) of varying size. It also covers related issues such as CAD navigation, data correlation, and the use of bitmap overlays for end-pointing.

3D X-ray tomography plays a critical role in electronic device failure analysis, but it can take several hours to overnight to get sufficient resolution in fault regions to detect and identify defects. In this paper, we propose a machine learning based reconstruction technique that can speed up data acquisition by a factor of four or more, while maintaining image quality. The method, which uses neural networks, extracts signals from low-dose data more efficiently than the conventional Feldkamp-Davis-Kress (FDK) approach, which is sensitive to noise and prone to aliasing errors. Several semiconductor packages and a commercial smartwatch battery module are analyzed using the new technique and the results compared with those obtained using conventional methods. The neural network can be trained on as little as one tomography image and the only requirement for the training data is that the sample or region of interest is well represented with all characteristic features in the field-of-view.

Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.

With manufacturers now capable of creating transistors in the 5-7 nm node range, the ability to isolate, inspect, and probe individual metal and via layers is of the utmost importance for defect inspection and design validation. These isolated layers can be inspected for defects via SEM, provide design validation, or tested with electrical probing for failure analysis. The work herein describes a functional workflow that enables manufacturers to perform this kind of sample preparation in an automated fashion using plasma focused ion beam (FIB) technology. The workflow is scalable and can be used in both lab and fabrication environments.

This paper presents a method for determining positional variation and offsets in high aspect ratio etches used in the production of 3D NAND devices. The method uses a 3D fiducial as a positional reference in the field-of-view, which not only allows for high precision tracking of features through the depth of the device, but also aids in the alignment of images when performing 3D reconstructions. The workflow is based on plasma dual beam diagonal milling, which allows users to characterize structures through the device stack at a much higher throughput/slice than conventional methods, enabling enhanced process monitoring and control.

This paper discusses the development of an automated cell layer counting process for preparing 3D NAND flash memory samples for TEM analysis. In an initial proof-of-concept, several line markings were inscribed on the test device in evenly spaced intervals in order to evaluate its helpfulness for a human operator. A more automated procedure was then developed in which cell layers were counted to a desired target layer starting from a reference layer set by the operator. At that point, the operator could begin preparing the TEM sample.

This paper describes how electron beam induced current (EBIC) analysis is used to determine the doping profile of p-n junctions and identify defective devices. The limitations of both chemical etching and EBIC are discussed as is the use of ion milling as a potential method for enhancing resolution. The findings in this paper add to the understanding of EBIC and provide insights to further improvements in its use in failure analysis.