Abstract Presentation slides from the ISTFA 2021 tutorial, “[Basics and Current Aspects of Scanning Electron Microscopy].”

Abstract IC camouflaging has been proposed as a promising countermeasure against reverse engineering. Camouflaged gates contain multiple functional device structures, but appear as a single layout under microscope imaging, thereby concealing circuit functionality. The recent covert gate camouflaging design comes with a significantly reduced overhead cost, allowing numerous camouflaged gates in circuits which improves resiliency against invasive and semi-invasive attacks. Dummy inputs are used in the design, but SEM imaging analysis has only been performed on simplified contact structures so far. In this study, we fabricated real and dummy contacts in different structures and performed a systematic SEM analysis to investigate contact charging and passive voltage contrast. Machine learning based pattern recognition was also employed to examine the possibility of differentiating real and dummy contacts. Based on our experimental results, we found that the difference between real and dummy contacts is insignificant, which effectively prevents SEM-based reverse engineering.

Abstract An experimental study was undertaken to determine the minimum level of leakage or shorting current that could be detected by electron-beam induced resistance change (EBIRCH) analysis. A 22-nm SRAM array was overstressed with a series of gradually increasing voltage biases followed by EBIRCH scans at 1 V and 2-kV SEM imaging until fins were observed. It was found that the fins of a pulldown device could be imaged by EBIRCH at just 12 nA of shorting current, representative of a soft failure. Stressing the sample at higher voltages eventually created an ohmic short, which upon further investigation, strongly suggested that the Seebeck effect plays a significant role in EBIRCH analysis.

Abstract This paper describes a procedure for preparing packaged GaN devices for photon emission microscopy from the backside, which has proven to be an effective method for isolating faults. The deprocessing technique was developed for GaN devices formed on thick p ++ silicon substrates mounted in quad-flat no-lead (QFN) packages connected by gold wires. It consists of mechanical polishing, which removes backside metal and packaging material, and selective etching, which quickly etches the silicon while leaving the gold wires intact for electrical measurements. The authors describe each step of the process in detail and explain how emission spots are marked with a UV laser and analyzed in a FIB-SEM system to determine the underlying cause of failure.

Abstract This paper presents a large-volume workflow for fast failure analysis of microelectronic devices. The workflow incorporates a stand-alone ps-laser ablation tool and a FIB-SEM system. As implemented, the picosecond laser is used to quickly remove large volumes of bulk material while the Xe plasma FIB provides precise end-pointing to the feature of interest and fine surface polishing after laser ablation. The paper presents several application examples, including a full workflow to prepare artefact-free, delamination-free cross-sections in an AMOLED mobile display and the preparation of devices and packages (including flip chips) of varying size. It also covers related issues such as CAD navigation, data correlation, and the use of bitmap overlays for end-pointing.

Abstract With manufacturers now capable of creating transistors in the 5-7 nm node range, the ability to isolate, inspect, and probe individual metal and via layers is of the utmost importance for defect inspection and design validation. These isolated layers can be inspected for defects via SEM, provide design validation, or tested with electrical probing for failure analysis. The work herein describes a functional workflow that enables manufacturers to perform this kind of sample preparation in an automated fashion using plasma focused ion beam (FIB) technology. The workflow is scalable and can be used in both lab and fabrication environments.

Abstract This paper presents a method for determining positional variation and offsets in high aspect ratio etches used in the production of 3D NAND devices. The method uses a 3D fiducial as a positional reference in the field-of-view, which not only allows for high precision tracking of features through the depth of the device, but also aids in the alignment of images when performing 3D reconstructions. The workflow is based on plasma dual beam diagonal milling, which allows users to characterize structures through the device stack at a much higher throughput/slice than conventional methods, enabling enhanced process monitoring and control.

Abstract This paper describes how electron beam induced current (EBIC) analysis is used to determine the doping profile of p-n junctions and identify defective devices. The limitations of both chemical etching and EBIC are discussed as is the use of ion milling as a potential method for enhancing resolution. The findings in this paper add to the understanding of EBIC and provide insights to further improvements in its use in failure analysis.

Abstract This paper evaluates the use of nanomilling and STEM imaging to analyze failure mechanisms in sub-50 nm InP HEMTS. The devices were life tested at elevated temperatures and biases and their electrical characteristics were measured at each stress interval. Devices that were damaged were investigated further to assess the underlying failure mechanism. Advanced microscopy with sub-nm resolution was employed to examine the physical characteristics of the failed HEMT devices at the atomic scale. As the paper explains, the examination was conducted using a focused ion beam/scanning electron microscope (FIB/SEM), an Ar gas ion nanomill, and STEM imaging.

Abstract This paper presents a method that allows top view SEM inspection on GaN devices previously subjected to PEM analysis from the backside and the associated sample preparation procedures. By filling the backside cavity with glob-top resin and epoxying the device to a piece of silicon, it is possible to remove all covering layers with a sequence of wet etches. A dried Ag liquid strap eliminates SEM charging problems and backside laser marks are made visible from the front side using an IR wavelength. The paper describes each step of the process in detail along with the results of the frontside SEM inspection.

Abstract Object localization is an essential step in image-based hardware assurance applications to navigate the view to the target location. Existing localization methods are well-developed for applications in many other research fields; however, limited study has been conducted to explore an accurate yet efficient solution in hardware assurance domain. To this end, this paper discusses the challenges of leveraging existing object localization methods from three aspects using the example scenario of IC Trojan detection and proposes a novel knowledge-based object localization method. The proposed method is inspired by the 2D string search algorithm; it also couples a mask window to preserve target topology, which enables multi-target localization. Evaluations are conducted on 61 test cases from five images of three node-technologies. The results validate the accuracy, time-efficiency, and the generalizability of the proposed method of locating multi-target from SEM images for hardware assurance applications.

Abstract This paper presents a failure analysis to determine the origin of the failure on the soldered balls of one BGA soldered to a Printed circuit board, presenting Intermittency on the soldered joints, by Visual inspection, X ray inspection, Computed Tomography(CT), Cross-section analysis, Scanning Electron Microscopy, and Energy dispersive spectroscopy, determined the failure located on soldered balls of the BGA was caused by cracks that run along the Intermetallic layer formed between the solder balls and the copper pads of the printed circuit board, that were located near the BGA corners. With X ray computed Tomography we can analyze all the soldered balls of the BGA, by "virtual" cross-sections on the soldered joints without damage on the sample.

Abstract Failure analysis plays a very important role in semiconductor industry. Photon Emission Microscopy (PEM) has been extensively used in localization of fails in microelectronic devices. However, PEM emission site is not necessarily at the location of the defect. Thus, it has limitation for the success rate of the follow-up physical failure analysis focusing on the emission site. As semiconductor technology advanced in the 3D FinFET realm and feature size further shrank down, the invisible defects during SEM inspection are tremendously increased. It leads to the success rate further decreasing. To maintain good success rate of failure analysis for advanced 3D FinFET technology, electrical probing is necessary to be incorporated into the failure analysis flow. In this paper, first, the statistic results of PEM emission sites versus real defect locations from 102 modules of microprocessors manufactured by 14nm 3D FinFET technology was present. Then, we will present how to wisely design electrical probing plan after PEM analysis. The electrical probing plans are tailored to different scan chain and ATPG failures of microprocessors for improving failure analysis success rate without increasing too much turn-around time. Finally, two case studies have been described to demonstrate how the electrical probing results guide the follow-up physical failure analysis to find the defect.

Abstract Passive voltage contrast (PVC) is widely used to detect underlying connectivity issues between metals based on the brightness of upper metals using scanning electron microscopy (SEM) or focused ion beam (FIB). [1] However, it cannot be applied in all cases due to the uniqueness of each case where brightness alone is insufficient to tell leakage location. In this study, propose a simple technique using platinum (Pt) marking as a circuit edit (CE) technique to alter metal PVC to identify the actual leakage location. Conventional SEM and PVC contrast imaging are unable to pinpoint exact defects without data confirming the leakage from nano-probing such as Atomic Force Probing (AFP) or SEM base nano-probing (NP) [2]. Using this method, we can improve the analysis cycle time by direct analysts the defective location in SEM, while also saving tool cost.

Abstract A protocol for obtaining an advanced TEM lamella geometry using FIB-SEM is presented. Lamella lift-out procedure might require multiple manipulation steps or even breaking the vacuum in order to reach inverted or plan-view lamella geometries. We have developed a setup which enables lamella transfer from a bulk sample onto a TEM grid within a single, very simple manipulation step, with no need to break the vacuum or unload the sample. Most importantly, this approach does not require any additional devices to be installed.

Abstract Advanced packages such as 2.5D will continue to grow in demand as performance increases are needed in various applications. Failure analysis must adapt to the changes in the interfaces, materials and structures being developed and now utilized. Traditional techniques and tools used for selectively removing materials to isolate and analyze defects need to evolve alongside these packages. A CF4-free Microwave Induced Plasma (MIP) process is used to remove underfill (UF) with minimal alteration of other materials on the samples, a process which has become more difficult on 2.5D modules. UF is removed using this MIP process to allow subsequent analysis on interposer interconnects and ìbumps in crosssection. SEM inspection, Electron Beam Absorbed Current (EBAC), and FIB are techniques used post cross-sectional UF removal of these 2.5D structures. The benefits of the specific MIP process through case studies are presented. Specifically, the use of an automatic cleaning step and a CF4-free downstream O2 plasma allow easy removal of UF without damaging other structures of interest with little tool recipe development.

Abstract Understanding solder joints is very important for failure analysis in semiconductor manufacturing because it is commonly used for mounting semiconductor devices on boards. However, regarding sample preparation for analysis, solder poses challenges in crosssection preparation due to the differences in melting point and hardness of its constituents. Therefore, precision cutting methods such as ion milling are required. On the other hand, ion milling method usually causes thermal damage during cutting. In this paper, we tried to optimize the sample temperature during Ar ion milling using liquid nitrogen cooling [1].

Abstract With the ever shrinking semiconductor device features coupled with the increasing circuit density, optical level fault localization techniques such as Photon Emission Microscopy (PEM), Laser Signal Injection Microscopy (LSIM) and Thermal Hotspot Localization (THS) can only get you so far due to these limitations: magnification, spot size and drop in detection sensitive at higher magnification. Using a 100x objective can put you in the ball park. Test data such as ATE & ATPG can point you to a specific block of circuitry but still far from defect localization. With in-SEM fault isolation and localization techniques such as Voltage Contrast (VC), Electron Beam Induced/Absorb Current (EBIC/EBAC) and Resistive Contrast Imaging (RCI), the nano-scale defect can be further localized due to the advantage of the magnification and spot size. This paper offers the combined techniques of optical level fault localization (PEM, LSIM & THS) and in- SEM or E-beam techniques (VC, EBAC, RCI) to successfully perform fault localization when challenged with the above scenarios.

Abstract Lock-in thermography (LIT) has been successfully applied in different excitation and analysis modes including classical LIT, analysis of the time-resolved temperature response (TRTR) upon square wave excitation and TRTR analysis in combination with arbitrary waveform stimulation. The results obtained by both classical square wave- and arbitrary waveform stimulation showed excellent agreement. Phase and amplitudes values extracted by classical LIT analysis and by Fourier analysis of the time resolved temperature response also coincided, as expected from the underlying system theory. In addition to a conceptual test vehicle represented by a point-shaped thermal source, two semiconductor packages with actual defects were studied and the obtained results are presented herein. The benefit of multi-parametric imaging for identification of a defect’s lateral position in the presence of multiple hot spots was also demonstrated. For axial localization, the phase shift values have been extracted as a function of frequency [4]. For comparative validation, LIT analyses were conducted in both square wave and arbitrary waveform excitation using custom designed and sample-specific stimulation signals. In both cases result verification was performed employing X-ray, scanning electron microscopy (SEM) and energy dispersive x-ray (EDX) as complementary techniques.

Abstract This research sets up failure analysis flow to verify failure mechanisms and root causes of different kinds of contact leakage. This flow mainly uses EBIC, C-AFM and nano-probing to do fault isolation and confirm electrical failure mechanisms. Appropriate sample preparation is also mandatory for FIB, SEM and TEM inspection.