Abstract Focused Ion Beam (FIB) chip circuit editing is a well-established highly specialized laboratory technique for making direct changes to the functionality of integrated circuits. A precisely tuned and placed ion beam in conjunction with process gases selectively uncovers internal circuitry, create functional changes in devices or the copper wiring pattern, and reseals the chip surface. When executed within reasonable limits, the revised circuit logic functions essentially the same as if the changes were instead made to the photomasks used to fabricate the chip. The results of the intended revision, however, can be obtained weeks or months earlier than by a full fabrication run. Evaluating proposed changes through FIB modification rather than proceeding immediately to mask changes has become an integral part of the process for bringing advanced designs to market at many companies. The end product of the FIB process is the very essence of handcrafted prototyping. The efficacy of the FIB technique faces new challenges with every generation of fabrication process node advancement. Ever shrinking geometries and new material sets have always been a given as transistor size decreases and overall packing density increases. The biggest fundamental change in recent years was the introduction of the FinFET as a replacement for the venerable planar transistor. Point to point wiring change methodology has generally followed process scaling, but transistor deletions or modifications with the change to Fins require a somewhat different approach and much more careful control due to the drastic change in height and shape. We also had to take into consideration the importance of the 4 th terminal, the body-tie, that is often lost in backside editing. Some designs and FET technology can function acceptably well when individual devices are no longer connected to the bulk substrate or well, while others can suffer from profound shifts in performance. All this presents a challenge given that the primary beam technology improvements of the fully configured chip edit FIB has only evolved incrementally during the same time period. The gallium column system appears to be reaching its maximum potential. Further, as gallium is a p-type metal dopant, there are limitations to its use in close proximity to certain active semiconductor devices. Amorphous material formation and other damage mechanisms that extend beyond what can be seen visually when endpointing must also be taken into account [1]. Device switching performance and even transmission line characteristics of nearby wiring levels can be impacted by material structural changes from implantation cascades. Last year our lab participated in a design validation exercise in which we were asked to modify the drive of a multi-finger FinFET device structure to reduce its switching speed impact on a circuit. The original sized device pulled the next node in the chain too fast, resulting in a timing upset. Deleting whole structures and bridging over/around them is commonly done, but modifications to the physical size of an FET device is a rare request and generally not attempted. It requires a level of precision in beam control and post-edit treatment that can be difficult to execute cleanly. Once again during a complex edit task we considered the use of an alternate ion beam species such as neon, or reducing the beam energy (low kV) on the gallium tool. Unfortunately, we don’t yet have easy access to a versatile viable replacement column technology grafted to a fully configured edit station. And while there should be significantly reduced implant damage and transistor functional change when a gallium column FIB is operated at lower accelerating potential [2], the further loss of visual acuity due to the reduced secondary emission, especially when combined with ultra-low beam currents, made fast and accurate navigation near impossible. We instead chose the somewhat unconventional approach of using an ultra-low voltage electron beam to do much of the navigation and surface marking prior to making the final edits with the gallium ion beam in a dual-beam FIB tool. Once we had resolved how to accurately navigate to the transistors in question and expose half of the structure without disturbing the body-tie, we were able to execute the required cut to trim away 50% of the structure and reduce the effective drive. Several of the FIB modified units functioned per the design parameters of a smaller sized device, giving confidence to proceed with the revised mask set. To our surprise, the gallium beam performed commendably well in this most difficult task. While we still believe that an inert beam of similar characteristics would be preferable, this work indicates that gallium columns are still viable at the 14 nm FinFET node for even the most rigorous of editing requirements. It also showed that careful application of e-beam imaging on the exposed underside of FinFET devices could be performed without degrading or destroying them.

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

Abstract Backside FIB circuit edit is an effective way to modify circuit on flip chip or stacked chips. Directly damaging memory cell through bulk silicon by FIB can be used to locate bit address to verify that the scramble test program coordinates correspond to the physical cell location. This paper presents the application of FIB for chip editing, discusses the limitation of the FIB approach and reports the scramble test experiments about the front-side and backside FIB technique to correct scramble testing data.

Abstract Direct measurements of circuit node signals without changing the performance of the circuitry are essential in modern FA but often impossible for recent IC technologies. This paper shows new methods, based on FIB backside circuit edit, allowing access to every existing circuit node at the device level, and discusses options for probing and discrete characterization.

Abstract It is shown in this study that it is possible to modify under a controlled way the resistance of a passive component either through the milling of part of the volume of a polysilicon resistor or on the contrary through the deposition of a Pt strap parallely connected to the involved device polysilicon resistor. In the latter case, each modification step being followed by an electrical characterization, the evolution of device VCO phase noise versus equivalent resistor value could be drawn and the optimum value quantified.

Abstract Focused Ion Beam (FIB) success has become more difficult as microchip process technology advances, requiring new techniques for damage control both during the microsurgery procedure and before the finished product can be electrically tested. Ultra thin gate dielectrics, shallower junctions, less ‘white space,’ and new materials surrounding active devices all create additional challenges for imaging, targeting, controlling instantaneous charge damage, and the removal of residual implanted charge. On the macro level, global thinning of bulk silicon housed in hybrid packages is causing new problems with thermal management and mechanical stress. Techniques and procedures used to control electrostatic discharge type damage become ever more critical when working on poorly buffered or isolated device elements, especially from the backside. Implanted gallium and residual charge perturb electrical characteristics, and must be dispersed prior to power-up thru carefully controlled bake steps. Left in place, these FIB-induced perturbations are likely to cause poor functionality or even latchup. The mechanical rigidity and thermal dissipation properties of newer, complex package types must also be restored post-FIB, otherwise cracked silicon or a thermal overload event might be the outcome. In this paper, we will attempt to address some of the common causes of FIB-induced failure on newer silicon and package technologies, and how they might be overcome. FIB techniques and preparatory processes must continue to evolve in order to deal effectively with the problems of direct beam damage, residual charge elimination, and sample stress management.

Abstract In-line repair of same-level killer defects is suggested as a method of the future for achieving higher yields. A methodology describing selection of killer defects and how to repair them is presented. A proof of concept experiment is presented where killer defects are removed from comb test structures using a FIB. An economic analysis is also included which indicates that this technique is economically viable for more costly chip designs. Therefore additional development work is merited.

Abstract Gas Assisted Etching (GAE) is the enabling technology for High Aspect Ratio (HAR) circuit access via milling in Focused Ion Beam (FIB) circuit modification. Metal interconnect layers of microelectronic Integrated Circuits (ICs) are separated by Inter-Layer Dielectric (ILD) materials, therefore HAR vias are typically milled in dielectrics. Most of the etching precursor gases presently available for GAE of dielectrics on commercial FIB systems, such as XeF2, Cl2, etc., are also effective etch enhancers for either Si, or/and some of the metals used in ICs. Therefore use of these precursors for via milling in dielectrics may lead to unwanted side effects, especially in a backside circuit edit approach. Making contacts to the polysilicon lines with traditional GAE precursors could also be difficult, if not impossible. Some of these precursors have a tendency to produce isotropic vias, especially in Si. It has been proposed in the past to use fluorocarbon gases as precursors for the FIB milling of dielectrics. Preliminary experimental evaluation of Trifluoroacetic (Perfluoroacetic) Acid (TFA, CF3COOH) as a possible etching precursor for the HAR via milling in the application to FIB modification of ICs demonstrated that highly enhanced anisotropic milling of SiO2 in HAR vias is possible. A via with 9:1 aspect ratio was milled with accurate endpoint on Si and without apparent damage to the underlying Si substrate.

Abstract Precision detection of endpoint after the milling has reached targeted conductor during circuit modification by focused ion beam system is important. While the sensitivity of the endpoint detection can be enhanced by improved secondary electron collection and sample absorbed current monitoring, a detailed understanding of the endpoint signal distribution within a high aspect ratio (HAR) via is of great interest. This article presents an alternative model of HAR via milling endpointing mechanism in which a phenomenon of spatial distribution of the endpoint information within the HAR via is explained based on sputtering of the material from the targeted metal line and redeposition of the spattered material on the via sidewalls. Increased emission of the secondary electrons, resulting from the subsequent bombardment of this conductive re-deposition by the primary ion beam, is detected as the endpoint. A methodology for the future experimental verification of the proposed model is also described.

Abstract Secondary electron signal is widely used in Focused Ion Beam (FIB) systems for imaging and endpointing. In the application of integrated circuit modification, technology has progressed towards smaller dimensions and higher aspect ratios. Therefore, FIB based circuit modification processes require the use of primary ion beam currents below 10 pA and Gas Assisted Etching (GAE). At low beam currents, short pixel dwell times and high aspect ratios, the level of available secondary electrons for detection has declined significantly. FIB GAE and deposition requires delivery and release of a gaseous agent near the beam scanning area, and involves insertion of a gas delivery nozzle made of conductive material and grounded for charge prevention purposes. The proximity of a grounded gas delivery nozzle to the area being milled and/or imaged creates a “shielding” effect, further lowering secondary electron signal level. The application of a small positive bias to the gas delivery nozzle provides an effective way of reducing the “shielding” effect. Depending on the geometrical arrangement of the gas delivery system and other conductive objects in the chamber, an optimized nozzle bias potential can create conditions favorable for enhanced extraction and collection of secondary electrons. The level of the secondary electron image signal, collected in an FEI Vectra 986+ system, from a grounded copper sample with the nozzle extended and biased can be enhanced as much as six times as compared to the grounded nozzle. Secondary electron intensity endpoint is improved on backside samples, however shielding of the nozzle field by the bulk silicon substrate limits the electron extraction effect from within a via. For front side edits the improvement of endpoint signal level can be dramatic. Lateral image offset induced by the electrostatic field of a biased nozzle, can be removed by software position compensation.

Abstract The use of FIB in circuit modification can generate huge influences on MOS transistor parameters. It is necessary to investigate and understand the effects that occur after Ga irradiation to evaluate the influence on the behaviour of the modified structures. In this paper we investigate influences on the threshold voltage of an n-FET MOS transistor in a standard, state of the art 0.17 µm DRAM technology, after FIB irradiation. In particular, the effect of varying the distance (vertical and horizontal) between the location of the FIB modification and the active area as well as the possibility of recovering the induced Vth shift has been characterized.

Abstract Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.

Abstract While integrated circuits are routinely modified using Focused Ion Beam systems (FIB), the reliability of these modifications has not yet been thoroughly studied. For several years, researchers at Sandia National Labs and CNES have been involved in the evaluation of the impact of FIB exposure on semiconductor structures. We have all come to the same conclusion: the intrinsic behavior of a circuit is altered after FIB intervention and the damage cannot be completely recovered but can be controlled. Despite these results, modified circuits are used in many applications such as satellites or even more critical environments. Although FIB modifications are invasive to the circuit they provide a working sample that can prove out, in silicon, a design change. However, is the functionality of FIB modified ICs reliable? In more practical terms: Can we use modified devices for our applications and what guarantee do we have that they will work after a few months? To answer these questions, we have conducted extended studies addressing both MOS and bipolar circuits. We used basic structures (such as transistors and diodes) and complex structures (operational amplifiers, oscillators, etc) and studied the effects of two different FIB systems, a Schlumberger P2X and an FEI Vectra 986. We have investigated the reliability of the devices by monitoring intrinsic parameters, before FIB, after FIB, during life testing and after life testing.

Abstract Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.

Abstract Focused Ion Beam (FIB) is used to modify a ring-oscillator circuit to enable the direct characterization of AC hot-carrier effects. Probe access to internal device nodes is necessary to find out the amount of individual device degradation resulting from AC hot-carrier stress. The circuit modification on an existing wafer by FIB enables the direct measurement of individual device in the circuit before and after AC hotcarrier stressing without resorting to new mask sets and silicon wafer processing for new hotcarrier reliability test circuits that can provide realistic stress voltage waveform. Small pads produced by FIB have small acceptable impact on the stress waveform of the circuit and they still allow accurate measurement of the internal device nodes. FIB’s ‘cut and paste’ technique is used to form these probe pads. Some suggestions are made for the proper FIB work in this paper. The results of AC hot-carrier tests with the circuit modified by FIB are also presented with some illustrative figures.

Abstract The task of circuit repairing and debugging using a Focused-Ion-Beam system on multi-layered IC devices is often difficult and tedious, especially when desired or target metal nodes or layers are buried under other higher level or nontarget metal nodes or layers. As a result, not only are target nodes difficult to access, but also, undesired shorts are difficult to prevent. To further complicate the situation, as the number of metal layers increases, the lower level metal nodes become increasingly thinner, and the node population becomes increasingly denser. These conditions result in a decreased success rate utilizing the FIB and an increased turn-around time for design debugging. Besides significant improvement of the FIB equipment and tools, new techniques that can be used to overcome the difficulties encountered during FIB operations on multi-layered IC devices need to be utilized. In this paper, we will focus on discussion of some new techniques that can be used for FIB device modification work and device debugging on multi-layered IC devices, including C4 (controlled-collapse chip connection) flip-chip devices. Some recommendations and tips for using these techniques on complicated fib modification work will also be shared based on the author’s experience.

Abstract Recent planar technologies with 3 metal layers or more challenge current physical design modification capacities using Focused Ion Beam tools. Image visibility on the FIB is drastically reduced, making accurate positioning and milling operations in the area of interest more difficult, and the use of power planes increases the risk of short circuits while accessing inferior metal lines. Despite the complexity of FIB modifications, however, the demand for circuit modifications continues to increase. To respond to this demand for successful, time efficient, FIB modifications, step by step monitoring of operations is imperative. In this paper, we will present an innovative method which brings in-situ electrical monitoring and contactless measurement capabilities to FIB systems. Electrical connection of the circuit inside the vacuum FIB chamber is done using a commercial load module and logic waveform acquisition with the FIB is obtained without modifying FIB hardware using a voltage contrast approach. With this method, it is possible to verify the completion of FIB milling and depositing operations by temporarily suspending FIB action so that a test pattern can be run allowing electrical testing and measurements of the circuit without damaging it.

Abstract Copper will probably replace aluminum alloys as the interconnect metallurgy of choice for high performance semiconductor devices. This transition will challenge the suitability of established practices in focused ion beam (FIB) chip repair. A fundamental rethink in methodology, techniques, and process gases will be required to deal with the new metal films. This paper discusses the results of recent experiments in the areas of FIB exposure, cuts and connections to buried copper lines. While copper tends to mill faster than aluminum, etch rate variations due to grain structure tend to make reliable isolation cuts more difficult. The films also have been shown to suffer regrowth and surface reactions during long term storage following FIB exposure. Attempts at halogen gas assisted etch (GAE) mills result in undesirable removal characteristics, and in the case of bromine, the spontaneous destruction of all exposed copper in the immediate area. Resistance measurements and reliability of deposited tungsten connections to copper lines are also presented. In addition, the latest techniques developed for aluminum wiring isolation and device characterization are shown. These include 'cleanup' methods for achieving good circuit isolation without the extensive use of local oxide deposition, and the latest multilevel version of the FIB ‘wagon wheel’ for SRAM cell characterization. Also included is preliminary data from a custom built FIB chamber four manipulator prober module.

Abstract Focused Ion Beam (FIB) surgery techniques need to develop to match the new challenges. One area for performance enhancement is in the deposition of lower resistivity conducting materials. At the present time, the two most commonly used materials for conductive deposition are Platinum and Tungsten. The main issue concerning these two materials is the relatively high resistivity of the deposited material; the deposited film can have 100 to 200 times the resistivity of the pure material. FIB-induced deposition of gold films have been commonly used in the repair of masks. In this application the resistivity of the deposited sample is of little importance. An examination of C 7 H 10 AuF 3 O 2 (t-fac) as a precursor gas shows that its resistivity when deposited with a FIB is 4-5 times lower than that of Platinum or Tungsten. The deposition rate is also significantly quicker. No electric-migration and dendrite formation was noticed after the Gold deposition was subjected to continuous current flow. However, the thermal stability of the pre-cursor gas is low and will need further refinement. (1,2,6)

Abstract This paper explains how laser assisted deposition used in combination with focused ion beam (FIB) milling reduces turnaround time for complex circuit modifications. It presents the results of three case studies, characterizing the process and the effect of various processing parameters. The first case involves the creation of a low resistance path between internal signal lines using only laser techniques; the second case demonstrates the use of laser deposition to route interconnects, millimeters in length, between two complex FIB modifications; and the third case is designed to reproduce a charge build-up problem. The paper also discusses the use of gold as a deposition material.