This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers passive voltage contrast (PVC), nanoprobing, conductive atomic force microscopy, and photon emission microscopy (PEM). It describes signal types, how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

Traditionally, reliability defects are addressed by end-of-line electrical measurements and extensive and dedicated testing during packaging. These tests cover almost every known defect condition and ensure product reliability with high confidence, but they occur in the final stage of manufacturing and are quite time intensive. This paper shows that inline reliability metrology based on Raman spectroscopy is an effective approach for early fault detection and can be used to monitor unintended epi growth, strain, lattice defects, stacking faults, dislocations, and post-etch residues. It can also reveal process anomalies and potential material problems. The paper examines the relationship between process parameters and reliability and reviews the enablers of preventive, early-detection inline metrology in the fab.

In this paper, we describe the difference between oscilloscope pulsing tests and waveform generator fast measurement unit (WGFMU) tests in analyzing high-resistance defects in DRAM main cells. Nanoprobe systems have various constraints in terms of pulsing whether it involves an oscilloscope or pulse generator. There are certain types of devices, such as DRAM cells, for which these systems are ineffective because saturation currents are too small. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in combination with an electro-optical nanoprobe.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers electron beam absorbed current (EBAC), electron beam induced current (EBIC), passive voltage contrast (PVC), optical and electron beam induced resistance change methods (OBIRCH and EBIRCH), lock-in thermography, photon emission microscopy (PEM), and nanoprobing. It describes how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

In this work, two analysis methods for word line (WL) defect localization in NAND flash memory array are presented. One is to use the Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH) to analyze the device through backside, which has no risk of damage during sample preparation. Depending on the I-V characteristics of defects, different analysis tools can be applied. The second method is to analyze a device defect location that is hard to detect through backside analysis. The precise defect site can be localized by Electron Beam Induce Resistance Change (EBIRCH) [1,2], and the defect profile can be observed. The large memory array in NAND flash structure leads to the wide sample movement during EBIRCH analysis. The sub-stage movement function used successfully solves this problem.

The global radio frequency (RF) semiconductor market size is growing dramatically in recent years, especially with the growing demand for mobile devices, communication networks, automotive applications, etc. Failure analysis (FA) on RF devices is normally more complex than digital devices, especially when it involves soft failure. This paper discusses FA on an RF product soft failure issue by the pulsed currentvoltage (IV) nanoprobing technique. The device suffered from high-frequency failure and exhibited abnormal repetitive softstart signature. Previous publications on pulsed IV nanoprobing applications were mostly related to Front End Of Line (FEOL) issues and simulations. In most of these cases, the electrical abnormality could also be observed with normal DC IV measurement. In this paper, the pulsed IV nanoprobing was performed at the Back End Of Line (BEOL) interconnects to isolate the failure that was otherwise not detected with normal DC nanoprobing or the reported pulse IV measurement. The proposed method successfully isolate, simulate the failure, and helping us to identify the process and design rule weakness.

As scaling-down of dynamic random access memory (DRAM) has been continued, the pitch of metal-line already reached sub-50nm where it is hard to define the soft bridge and normal one. Moreover, the metal bridge failure at system level cannot be corrected with in-situ system error-code correction (ECC) modules. In order to screen these failures in the wafer or/and package level electrical tests, high voltage stress methods are necessary. Therefore, accurate stress quantity decided by combination temperature, voltage and time, and effective stress methodologies are essential for high quality and reliability. For a mass production environment, a wafer level burn-in (WBI) can enable multiple word-lines simultaneously and consistently is appropriate. Moreover, we confirmed the actual voltage level on real cells in WBI and optimized stress parameters in terms of time and voltage. Finally, it was proven through the WBI evaluation for over 60k DRAM chips.

Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

For a recent replacement metal gate (RMG) technology using a SOI substrate, residue from the dummy gate formed a defect that affected the RMG formation. In this FINFET technology, the high aspect ratio of the gate makes removing the dummy gate very difficult. Residue is left behind, especially in multi-fin structures. This residue was poorly detected by existing Broad-Band-Plasma inspection and thus required Electron Beam Inspection. However, this physical inspection is challenging due to high aspect ratio of the gate and an insulating wafer surface. The defect was verified using TEM, and careful sample prep is shown to be critical to verify the defect. The high aspect ratio and insulating sample in a charged-particle inspection is investigated with Monte-Carlo (MC) simulations.

Systematic retention failure related on the adjacent electrostatic potential is studied with sub 20nm DRAM. Unlike traditional retention failures which are caused by gate induced drain leakage or junction leakage, this failure is influenced by the combination of adjacent signal line and adjacent contact node voltage. As the critical dimension between adjacent active and the adjacent signal line and contact node is scaled down, the effect of electric field caused by adjacent node on storage node is increased gradually. In this paper, we will show that the relationship between the combination electric field of adjacent nodes and the data retention characteristics and we will demonstrate the mechanism based on the electrical analysis and 3D TCAD simulation simultaneously.

Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

Elementally characterizing intermetallic compounds (IMCs) to identify phases has routinely required relatively expensive transmission electron microscopy (TEM) analysis. A study was done characterizing IMCs using less expensive energydispersive x-ray (EDX) spectroscopy tools to investigate it as a practical alternative to TEM. The study found that EDX line scanning can differentiate phases by tracking changes in count rate as the electron beam of a scanning electron microscope (SEM) passes from one phase to another.

E-beam Inspection (EBI) is used for in-line detection of defects in semiconductor manufacturing. This paper highlights a physical defect mode application where traditional defect inspection techniques, such as broadband plasma and dark field inspection were ineffective in finding the defects of interest. It describes the inspection setup and verification with failure analysis and the application of the technique. This inspection was implemented as a process monitor to detect excursions. The amount of process "ON" time after an etch-chamber part's change was identified as the main factor in MOAT defectivity. The correlation between EBI defect detection and leakage at in-line electrical test was further investigated by looking at each individual die and the leakage associated with the MOAT only. It was observed that the increased leakage could be due to another process factor in the process than a MOAT etch or a MOAT defect that was missed during the EBI inspection.

The open bit line architecture scheme is an effective method to achieve higher density memory devices. With the scaling of DRAM, we have adopted a bit line sense amplifier (BLSA) design using a shared local power line for reducing the circuit layout dimensions. As a result of this new design, the write time of the memory cell was sometimes degraded because of an increase in initial sensing noise. This paper gives a detailed analysis of the problem caused by the initial sensing noise by examination of the behaviour of the opposite data portion of the cell array matrix when the word line is not activated. Finally, we propose a design improvement to reduce the magnitude of noise peaks and the results of this improvement when implemented in the test vehicle.

Leakage current from bit line to SNC (Storage Node Contact) is one of the most critical issues in DRAM operation. Such failure becomes more difficult to visualize as the device shrinks. In this study, bit line to SNC leakage fail was analyzed using nano-probing tool in 2xnm DRAM technology.

Process defects, either random or systematic, are often the top killers of any semiconductor device. Process defect learning and reduction are the main focuses in both technology development stage and product manufacturing yield ramp stage. In order to achieve fast defect learning, in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding the defects which really cause device functional failures. However, often, the defects found by failure analysis are very different from the original defects, making it difficult to understand the root cause. This paper will describe a methodology how to combine in-line defect inspection and failure analysis together to found the top killer defects and accelerate their root cause identification for fast defect learning and yield improvement.

Transmission line analysis is done in electrical failure analysis labs in order to find root causes that result in system level failures. After a fault is narrowed to a particular signal in a system, a Time Domain Reflectometer (TDR) can be used to analyze the physical transmission line associated with the signal. The transmission lines on smartphones often have inaccessible signal vias, few or no ground vias, probe points that are difficult to see, and short transmission lines. One solution that can alleviate these problems is to design a TDR Accessory Card. This paper discusses the processes involved in testing long and short transmission lines, providing the comparison between the expected and actual TDR measurement and the advantages and disadvantages of TDR, explaining four main points for using a TDR Accessory Card and two reasons for not using the TDR Accessory Card.

The presence of a full wafer dual-beam FIB on the process floor gave rise to an environment in which formerly segregated off-line lab and FAB tasks could be linked. One such idea involved a methodology for semi-automated defect targeting based on the spatial predictions of static random access memory (SRAM) electrical testing. The embedded memory blocks on some processors are fully configured and probe pad testable as early as the forth metal level. Using a unique navigation technique that combines electrically sorted SRAM bit map data with CAD coordinate information and stage driven X-Y stepping, the FIB tool was used to locate, section and image prior level defects. We believe that with the inclusion of suitable fiducial markers in the chip design and advanced pattern recognition to aid navigation and guide depth milling, a fully automated process for electrical yield detractor diagnosis could be introduced.

One issue that faces failure analysis at the system level is impedance mismatched transmission lines resulting from developers pushing the edge of trace layout recommendations. When transmission lines on printed circuit boards are routed in such a way as to allow for impedance mismatches, the effects can be unwanted on the signal that the line carries. Techniques can be used for discovering if capacitance, resistance, or split planes are creating the impedance mismatches that are resulting in the system level failure seen by the customer.

We compare different dc current-based integrated capacitance measurement techniques in terms of their applicability to modern CMOS technologies. The winning approach uses quadrature detection to measure mutual Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) capacitances. We describe our implementation of this approach, Quadrature-clocked Voltage-dependent Capacitance Measurements (QVCM), and its application to 45 nm node BEOL: wire capacitance variability measurements for analog design, and capacitive test structure to measure the effect of metal pattern density on Chemical-Mechanical Polishing (CMP) and Reactive Ion Etching (RIE).