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ISTFA2022, ISTFA 2022: Tutorial Presentations from the 48th International Symposium for Testing and Failure Analysis, f1-f104, October 30–November 3, 2022,
...-338-5151 800-336-5152 (U.S. and Canada) 800-368-9800 (Europe) Fax: 440-338-4634 Technique Selection for Front End of Line Defect Localization in Bulk Si FA Greg Johnson ZEISS Microscopy Pougkeepsie, NY, United States Objectives for this tutorial LOCALIZATION PVC NANOPROBING CAFM PEM ISTFA 2022...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 203-205, October 31–November 4, 2021,
... Abstract Traditionally, reliability defects are addressed by end-of-line electrical measurements and extensive and dedicated testing during packaging. These tests cover almost every known defect condition and ensure product reliability with high confidence, but they occur in the final stage...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 258-262, October 31–November 4, 2021,
... generator in combination with an electro-optical nanoprobe. DC measurement nanoprobe oscilloscope pulsing test pulse generator resistive word line defect waveform generator ISTFA 2021: Proceedings from the 47th International Symposium for Testing and Failure Analysis Conference October 31...
Proceedings Papers

ISTFA2021, ISTFA 2021: Tutorial Presentations from the 47th International Symposium for Testing and Failure Analysis, f1-f134, October 31–November 4, 2021,
... for Front End of Line Defect Localization in Bulk Si FA Greg Johnson ZEISS Microscopy Pougkeepsie, NY, United States OUTLINE 1) Why localize? 2) How to localize? 2 OUTLINE 1) Why localize? 2) How to localize? 3 [AMD Official Use Only] SRAM Leakage case study PROBLEM: Diode leakage in SRAM leakage test...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 42-45, November 15–19, 2020,
... Abstract In this work, two analysis methods for word line (WL) defect localization in NAND flash memory array are presented. One is to use the Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH) to analyze the device through backside, which has no risk of damage...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 219-225, November 15–19, 2020,
... nanoprobing applications were mostly related to Front End Of Line (FEOL) issues and simulations. In most of these cases, the electrical abnormality could also be observed with normal DC IV measurement. In this paper, the pulsed IV nanoprobing was performed at the Back End Of Line (BEOL) interconnects...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 264-266, November 15–19, 2020,
... Abstract As scaling-down of dynamic random access memory (DRAM) has been continued, the pitch of metal-line already reached sub-50nm where it is hard to define the soft bridge and normal one. Moreover, the metal bridge failure at system level cannot be corrected with in-situ system error-code...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 135-139, November 5–9, 2017,
... and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 380-385, November 5–9, 2017,
... Monte-Carlo simulations replacement metal gates sample preparation silicon on insulator In-line Electron Beam Inspection of high aspect-ratio RMG FINFET gate Richard F. Hafer, Oliver D. Patterson, Cathy Gow, Derek McKindles GLOBALFOUNDRIES 2070 Route 52 Hopewell Junction, NY 12533, USA Brian Yueh...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 91-93, November 6–10, 2016,
... Abstract Systematic retention failure related on the adjacent electrostatic potential is studied with sub 20nm DRAM. Unlike traditional retention failures which are caused by gate induced drain leakage or junction leakage, this failure is influenced by the combination of adjacent signal line...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 182-185, November 6–10, 2016,
... front end of line gate oxides interlayer dielectric thinning polysilicon scanning transmission electron microscopy xenon difluoride etching Physical Failure Analysis (PFA) Techniques For Front-End-Of-Line (FEOL) Defect Analysis 1Dirk Doyle, 2Fritz Christian Awitan, 1Lawrence Benedict 1Product...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 114-119, November 1–5, 2015,
... to investigate it as a practical alternative to TEM. The study found that EDX line scanning can differentiate phases by tracking changes in count rate as the electron beam of a scanning electron microscope (SEM) passes from one phase to another. energy dispersive X-ray spectroscopy failure analysis...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 205-210, November 1–5, 2015,
... Abstract E-beam Inspection (EBI) is used for in-line detection of defects in semiconductor manufacturing. This paper highlights a physical defect mode application where traditional defect inspection techniques, such as broadband plasma and dark field inspection were ineffective in finding...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 237-240, November 1–5, 2015,
... Abstract The open bit line architecture scheme is an effective method to achieve higher density memory devices. With the scaling of DRAM, we have adopted a bit line sense amplifier (BLSA) design using a shared local power line for reducing the circuit layout dimensions. As a result of this new...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 202-204, November 9–13, 2014,
... Abstract Leakage current from bit line to SNC (Storage Node Contact) is one of the most critical issues in DRAM operation. Such failure becomes more difficult to visualize as the device shrinks. In this study, bit line to SNC leakage fail was analyzed using nano-probing tool in 2xnm DRAM...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 241-245, November 9–13, 2014,
..., in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 391-395, November 9–13, 2014,
... Abstract Transmission line analysis is done in electrical failure analysis labs in order to find root causes that result in system level failures. After a fault is narrowed to a particular signal in a system, a Time Domain Reflectometer (TDR) can be used to analyze the physical transmission...
Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 113-116, November 14–18, 2010,
... Abstract The presence of a full wafer dual-beam FIB on the process floor gave rise to an environment in which formerly segregated off-line lab and FAB tasks could be linked. One such idea involved a methodology for semi-automated defect targeting based on the spatial predictions of static...
Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 196-201, November 14–18, 2010,
... Abstract One issue that faces failure analysis at the system level is impedance mismatched transmission lines resulting from developers pushing the edge of trace layout recommendations. When transmission lines on printed circuit boards are routed in such a way as to allow for impedance...
Proceedings Papers

ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 208-213, November 15–19, 2009,
... Abstract We compare different dc current-based integrated capacitance measurement techniques in terms of their applicability to modern CMOS technologies. The winning approach uses quadrature detection to measure mutual Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) capacitances. We...