With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in novel device form factors. Even though the lock-in thermal detection technique had been demonstrated as a useful debug technique to detect defects on packages or pin related fails on 3D stack-die configuration, it is difficult to apply this technique to do functional debug. This paper presents a novel base die debug technique with TSV wirebond for 3D stack-die devices. A comprehensive study on the base die debug flow with real failing cases is also presented. Base die debug techniques will need to continue to be innovated to provide complete debug solutions for such platform.

The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.

With the growing complexity and interconnect density of modern semiconductor packages, package level FA is also facing new challenges and requirements. 3D X-Ray Microscopy (XRM) is considered a key method to fulfill these requirements and enable high success FA yield. After a short introduction into the basic principles of lab-based X-Ray tomography, 2 different approaches of X-Ray investigations are discussed and an integration into the daily FA flow is proposed. In the first example, fault isolation on a fully packaged device is demonstrated using a stacked die device. In the second example, a newly developed sample preparation flow in combination with Nanoscale 3D X-Ray Microscopy for Chip-Package-Interaction and Back-end-of-line feature imaging is introduced.

When it comes to complex system-in-package (SiP) with a wide spectrum of materials and packaging structures integrated into a single module, decapsulation and the following failure analysis become extremely complex. Previous work published by the authors' group has demonstrated that a halogen-free microwave induced plasma (MIP) system has great advantage compared to the conventional techniques mentioned before. This paper explores the applicability of the halogen-free MIP on the most complex SiP module decapsulation. Applications in special structures in SiP include 3D stacked-die, gallium arsenide, surface acoustic wave (SAW) and bulk acoustic wave filters, and copper re-distribution layer. The halogen-free MIP decapsulation process can expose and preserve all the dies and passive components as well as the original failure sites, which proves to be key to ensuring a high success rate in SiP failure analysis.

Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel nondestructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper, we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.

Within this paper, the authors present an adapted FA flow for state-of-the-art Package Failure Analysis for 20nm technology and below. As a key aspect, three methods (EOTPR, 3D Xray & PFIB) are introduced as the next-gen FA standard methods for emerging package technologies such as TSV, u-pillar bumping and stacked-die devices. By showing different types of daily Package FA requests, the paper compares & discusses important factors such as turn-around-time (TAT), success yield and results quality. In the end, an outlook is given how recent developments on these techniques will help to establish a new standard FA flow.

Advances in electronic packaging are fueled by the insatiable appetite that consumers have for bandwidth in mobile appliances. The technological answer to this demand is increase the interconnect count and shrink the pitch, solder volume and height. The features of interest and the defects in these packages are becoming increasingly smaller. Consequently, the characterization of these defects becomes more challenging due to the smaller size and new material structures. New package structures must pass the JEDEC standard tests and a critical part of qualifying new packages as products is proper identification of the root cause of failures. Therefore, innovative solutions to correct the fundamental problems in the development process enable new package solutions to be brought to the market. In this paper we describe an alternative failure analysis workflow involving X-ray microscopy which offers several advantages over standard imaging techniques. The nondestructive nature of x-ray microscopy enables engineers to image parts throughout the entire environmental stress cycle for more accurate determination of the root cause of failures. Additionally, a larger number of interconnects may be sampled, defect isolation in z direction for stacked die packages is made easier and subsequent imaging techniques may be used to complement the data. Both 3 dimensional images of defects as well as 2 dimensional cross sections will be shown to effectively analyze the true root cause of failures.

The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

Lock-in Thermography in combination with spectral phase shift analysis provides a capability for non-destructive 3D localization of resistive defects in packaged and multi stacked die devices. In this paper a novel post processing approach will be presented allowing a significant reduction of measurement time by factor >5 in comparison to the standard measurement routine. The feasibility of the approach is demonstrated on a specific test specimen made from ideal homogenous and opaque material and furthermore on a packaged hall sensor device. Within the case studies the results of multiple single LIT measurements were compared with the new multi harmonics data analysis approach.

This paper will illustrate the procedures to physically isolate one die in a stacked-die configuration. This highly reliable, systematic method allows for failure analysis engineers of all levels to successfully isolate the die of interest for further investigation.

The Focused Ion Beam (FIB) technique of internal modification for chip repair, layout verification, and internal signal probe access has become an integral part of the process for bringing advanced products to market. The pervasive switch from wire bond connections to single component flipchip solder bump mounting on high value products has greatly aided the task of FIB editing by placing the bare backside silicon of the die within easy reach. FIB chip circuit access begins with task-specific sample preparation. The package opening and silicon prep process is well defined and quite robust when full thickness chips are mounted to simple ceramic carriers. Unfortunately, the introduction of flexible organic laminate substrates and the development of stacked die packaging has further complicated the process. Multi-chip packages containing combinations of full thickness and thinned chips may be present. They could be wire-bond connected, or use Through-Silicon Vias (TSV) for double sided attachment. Multiple heat treatment cycles joining together materials with vastly different coefficients of thermal expansion (CTE) may result in severe package warpage and stress. All of these conditions and possible combinations have served to invalidate key elements of the established sample preparation process, and made each presented case unique. As the FIB team works to develop new precision techniques for internal circuitry access, the greater semiconductor packaging development and failure analysis community has benefited from the introduction of new tooling and methodologies.

While transistor gate lengths may continue to shrink for some time, the semiconductor industry faces increasing difficulties to satisfy Moore’s Law. One solution to satisfying Moore’s Law in the future is to stack transistors in a 3-dimensional (3D) formation. In addition, the need for expanding functionality, real-estate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques. We describe in this paper innovations in Magnetic Field Imaging for FI which have the potential to allow 3D characterization of currents for non-destructive fault isolation at every chip level in a 3D stack.

Lock-in thermography and magnetic current imaging are emerging as the two image-based fault isolation methods most capable of meeting the challenges of short and open defect localization in thick, opaque assemblies. Such devices are rapidly becoming prevalent as 3D integration begins to ramp up production. This paper expands on previously published work with a qualitative comparison of the techniques on single chip and stacked die packages with known designed-in or FIB created defects.

Focused Ion Beam (FIB) modification for chip repair, layout verification, and internal signal probing has become an integral part of the process for bringing advanced products to market. As devices become more complex, with more levels of dense, thick upper power planes and tighter lower point-to-point wiring and device geometries, primary FIB access through the backside of the chip has become the only viable approach. And the pervasive switch to flip-chip solder bump mounting of chips to modules and chip to chip stacked die has made the backside editing approach ever more sensible by placing the unobstructed backside of the die within easy reach. Sample preparation for backside edit, however, has become a growing problem. Mechanical thinning of the silicon to speed trenching time can be problematic on highly stressed chips as there is a high risk of silicon cracking. Plus there are situations in which die strength must be preserved to enable the transfer of an edited die to a new substrate. While single point full thickness silicon editing has been demonstrated, the need to make multiple trenches for repetitive edits can be extremely time consuming when using conventional FIB bulk removal recipes. A single logic error often gets repeated in each core of a multi-core chip, and may need to be fixed at each location. Verification of existing SRAM and the introduction of embedded DRAM (eDRAM) for large blocks of L3 cache on high end microprocessors meant that the FIB lab would be called upon to provide layout checking services on a number of designs. Clearly, a better method for rapid mass silicon removal needed to be developed to keep multi-point backside editing viable. Through an extensive set of experiments we were able to develop a process that can sustain a removal rate of 10 million cubic microns of silicon per minute, enabling full thickness trenches in as little as 25 minutes. As will be shown, this preparation technique was successfully used to ensure the bit map descramble accuracy of multiple eDRAM array blocks in several cores, and to help evaluate test coverage.

It was already demonstrated, that the method of Lock-in Thermography (LIT) enables 3D localization of thermal active defects, e.g. electrical shorts and resistive opens, on die level and within fully packaged single and multichip devices [1,2]. The depth of a defect can be derived from phase shift measurements of the defective compared to a reference device For a general approach of this method, thermal modeling is used and verified by experimental data to investigate the internal heat propagation under periodic stimulation in correlation to the LIT measuring process. [3]. A basic requirement for the successful application of the method is a precise and reproducible measurement of both the thermal material properties of each material layer and the phase shift between the internal heat excitation and thermal response measured by LIT. Significant influences from the material and measurement setup to the detected phase shift have to be identified and taken into account. However, to identify and distinguish the relevant influences measurements with defined internal heat sources are necessary which are presented in this paper. First, the relationship between geometrical thickness of a material layer and the resulting thermal parameters for both homogeneous and heterogeneous materials are measured and discussed. A new measurement setup generating a defined point heat source will be presented to calibrate the LIT system for quantitative phase shift measurements and to determine the phase shift to thickness parameters of single material layers. In addition the variation of the phase shift caused by the defect geometry and the defect environment will be investigated. Finally, a case study is presented comparing the experimental results to the obtained results from a real stacked die device.

Access to critical die and package structures for failure analysis purposes is complicated in stacked die devices in small packages, such as thin plastic Lead Frame Chips Scale Packages also known as Quad Flat No Leads Packages. This paper discusses the failure analysis solutions developed to effectively access the areas of interest. It illustrates two different ways of analyzing the bottom die: a repackaging technique and a technique for accessing from the backside of the bottom die. One of the major concerns during the evaluations that had been addressed was the difficulty of removing the nonconductive die attach material in between the top and bottom die. This was resolved by a novel method of thermal decomposition of the material. Observations suggested that the die extraction process did not introduce surface oxidation or contamination that may have led to a bonding failure.

In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or ebeam to induce a parametric shift, which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. SIFT (Stimulus Induced Fault Test), RIL (Resistive Interconnect Localization) and SDL (Soft Defect Localization) can identify anomalies functionally using induced thermal gradients to the metal but does not address how to analyze embedded temperature sensitive defects inaccessible to the laser. 1,2,3,4 Stacked die and similar 3 dimensional (3D) devices complicate the analysis requiring destruction/removal of one or more die. This paper will show how to create quantifiable thermal gradients to a defect and triangulate the location of the defect in 1, 2, and 3 dimensions as follows: 1. Apply a differential temperature gradient across the device in each of the X,Y, and Z-axes. The defect is localized based on its measured response in the gradient as the gradient sweeps across. 2. Induce a gradient with a laser and use the measurement of DC power required to relate the distance to the defect from various locations in relation to a heat sink. 3. Measure the time of flight of the thermal propagation to a defect from known laser positions to triangulate the location of the defect.

It has been shown that microscopic Lock-in-Thermography (LiT) can be used for localization of electrical active defects like shorts and resistive opens in integrated circuits. This paper deals with the application of LiT for non-destructive failure analysis of fully packaged single and multi chip devices. In this case inner hot spots generated by the electrical defects typically can not be imaged directly because the mold compound or adhesives above are not IR transparent. Inner hot spots can only be detected by measuring the corresponded temperature field at the device surface. By means of failed and test devices will be shown, that LiT is sensitive enough to measure such temperature fields. In addition to the lateral localization of inner hot spots its depth can also be determined by measuring the phase shift between the electrical excitation and the thermal response at the device surface. Furthermore, the influence of the lock-in-frequency and mold compound thickness to lateral resolution and signal to noise ratio will be discussed. Using real failed single chip and stacked die devices two analysis flows were demonstrated to locate inner defects.

Stacked-die packaging was used to make an octal 20-bit analog-to-digital (A/D) converter by stacking two quad A/D converter die in a single 48-lead QFN (quad flat-pack, no leads) package. Reliability testing for product qualification initially failed only (biased) HAST test. Two failure mechanisms were identified. The first mechanism was silver ion migration at sensitive analog inputs due to high conductive die-attach fillets on the bottom die. The second mechanism was ILD delamination and passivation layer cracking due to spacer-attach stress on the surface of the bottom die. Electrical failure analysis was aided by a self test mode designed into the quad A/D converter. Package opening and other standard failure analysis techniques required some modification to accommodate the stacked-die package. This work points to critical stacked-die assembly steps, including conductive die-attach and nonconductive spacer-attach application, where effects of moisture, bias, and thermal stress must all be considered.

For stacked die package delamination inspection using C-mode acoustic microscope, traditional interface and thorough scan techniques cannot give enough of information when the delamination occurs in multi-interfaces, and echoes from adjacent interfaces are not sufficiently separated from each other. A thinner thickness in the stacked-die package could complicate C-mode scanning acoustic microscopy (CSAM) analysis and sometimes may lead to false interpretations. The first objective of this paper is to briefly explain the CSAM mechanism. Based on that, some of the drawbacks of current settings in detecting the delamination for stacked-die packages are presented. The last objective is to introduce quantitative B-scan analysis mode (Q-BAM) and Zip-Slice technologies in order to better understand and improve the reliability of detecting the delamination in stacked-die packages. Therefore, a large portion of this paper focuses on the Q-BAM and Zip-Slice data acquisition and image interpretation.