This presentation covers the basic physics needed to understand and to effectively apply backside IC analysis techniques to flip-chip packaged die. It describes the principles of light transmission through silicon and the factors that influence optical image formation from the backside of the wafer or die. It also provides information on the tools and techniques used to expose surfaces, regions, and features of interest for analysis. It describes the steps involved in CNC milling, mechanical grinding and polishing, reactive ion etching (RIE), laser microchemical (LMC) etching, and milling and etching by focused ion beam (FIB). It explains where and how each technique is used and quantifies the capabilities of different combinations of methods.

This presentation covers the basic physics needed to effectively apply backside IC analysis techniques to flip-chip packaged die. It describes the principles of light transmission through silicon and the factors that influence optical image formation from the backside of the wafer or die. It also provides information on the tools and techniques used to expose surfaces, regions, and features of interest for analysis. It describes the steps involved in CNC milling, mechanical grinding and polishing, reactive ion etching (RIE), laser microchemical (LMC) etching, and milling and etching by focused ion beam (FIB). It explains where and how each technique is used and quantifies the capabilities of different combinations of methods.

This paper aims to discuss the processes involved in establishing a more rapid approach in exposing the polyfuse and thin film fuse using the reactive ion etching, chemical deprocessing and parallel lapping techniques. The results proved that parallel lapping technique in combination with chemical deprocessing and reactive ion etching is a faster approach in exposing the physical status of the fuses.

Conductive-Atomic Force Microscopy (C-AFM) is a popular failure analysis method used for localization of failures in Static Random Access Memory (SRAM) devices [1-4]. The SRAM structure has a highly repetitive pattern where any abnormality in a failed cell compared to neighboring cells could be easily identified from its current image [5-7]. Unlike topographical imaging, the C-AFM requires the probe tip to be coated with a conductive layer in order to pick up the electrical signals from the device under test. The coating needs to be sufficiently thick as it would wear off after a certain amount of physical scanning. This additional coating on the AFM tip is essential but poses a limit to the tip radius curvature. The commercially available tip radius is approximately 35nm (DDESP-10 from Bruker) and the dimension is too large for imaging of 20nm technology device. However, the limitation could be alleviated by subjecting the sample surface to treatment prior to C-AFM imaging. The aim of this surface treatment is to ensure C-AFM tip maintains sufficient scanning contact with the tiny conductive (tungsten) structure of the sample in order to achieve distinct current image. The surface treatment is done by creating a receding Inter-Layer Dielectric (ILD) from its neighboring tungsten contact. The creation of the receding depth could be achieved by either wet etching or dry etching (Reactive Ion Etching, RIE). In this work, the surface treatments by these two methods have been investigated and the recipe is optimized to obtain a clear current image. The optimized recipe is then applied on actual failure analysis where three cases are studied.

Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

With gold prices steadily going up in recent years, copper wire has gained popularity as a means to reduce cost of manufacturing microelectronic components. Performance tradeoff aside, there is an urgent need to thoroughly study the new technology to allay any fear of reliability compromise. Evaluation and optimization of copper wire bonding process is critical. In this paper, novel failure analysis and analytical techniques are applied to the evaluation of copper wire bonding process. Several FA/analytical techniques and FA procedures will be discussed in detail, including novel laser/chemical/plasma decapsulation, FIB, wet chemical etching, reactive ion etching (RIE), cross-section, CSAM, SEM, EDS, and a combination of these techniques. Two case studies will be given to demonstrate the use of these techniques in copper wire bonded devices.

Although the overall spatial resolution of backscattered electron (BSE) imaging suffers in comparison to secondary electron (SE) imaging, its superior sensitivity to atomic number (Z) contrast and ability to image through overlying insulation levels can provide a complementary approach for imaging subtle buried defects. BSE enables the localization and imaging of embedded defects through overlying insulator levels without the risk of compromising them with reactive ion etch (RIE) or plasma etch exposure or by anisotropic wet chemical delayering process steps. Once the embedded defect is localized with BSE in situ, subsequent imaging by cross sectional Transmission Electron Microscopy (XTEM) combined with elemental analysis by energy dispersive X-Ray analysis (EDX) or electron energy loss spectroscopy (EELs) can be performed without the risk of introducing artifacts. In this work, BSE imaging was successfully employed to image embedded subtle defects in 32nm node technologies through overlying insulator films not possible with conventional SE imaging techniques.

We compare different dc current-based integrated capacitance measurement techniques in terms of their applicability to modern CMOS technologies. The winning approach uses quadrature detection to measure mutual Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) capacitances. We describe our implementation of this approach, Quadrature-clocked Voltage-dependent Capacitance Measurements (QVCM), and its application to 45 nm node BEOL: wire capacitance variability measurements for analog design, and capacitive test structure to measure the effect of metal pattern density on Chemical-Mechanical Polishing (CMP) and Reactive Ion Etching (RIE).

A packaged device based on a ball grid array or other design presents a challenge to the failure analyst. Accessing one of the metal levels from the topside requires decapsulation by either a wet, predominantly dry (RIE) or a completely dry (mechanical) treatment. To reveal the details of the gate including the gate oxide, new approaches to selective etch delineation by RIE are required. This article presents an automated sample preparation method for packaged microelectronic materials by combining plasma cleaning, ion beam etching, reactive ion etching and ion beam sputter coating. A single etch gas chemistry was effective in phase delineation by RIE. Future work to further delineate the gate oxides could support accurate metrology by means of FESEM rather than field emission transmission electron microscope.

Challenges in sample preparation for semiconductor failure analysis are always increasing as more complex material and smaller dimensions are required to meet the needs of the semiconductor industry. These changes require the constant need for more refined procedures in all areas of sample preparation, including mechanical polish. This paper presents a newly modified technique which increases the planarity at the critical edge of the sample and results in a larger planar region of interest. The novel method combines both a blocked reactive ion etching and a standard planar polish. It has proven to be a successful delayering technique and helpful in facilitating further analysis. This method has been verified on dies, wafer pieces, and dies thinned and attached to blank silicon for support. It is useful for increasing overall planarity and particularly helpful for the extreme edge.

The SiLK resins, composed of aromatic hydrocarbons, are a family of highly cross-linked thermoset polymers with isotropic dielectric properties. Patterning of SiLK for high aspect ratio copper interconnects has depended on reactive ion etching with oxygen/nitrogen gas mixtures. Reactive ion etching is therefore also accomplished with reducing plasmas such as nitrogen/hydrogen. An additional plasma cleaning step can be inserted after the reactive ion etching (RIE) step, so that any residual contamination is removed prior to imaging or final sputter coating. Automated sample preparation of microelectronic materials containing high and low-k dielectrics for FESEM is accomplished in this article by combining these techniques: plasma cleaning, ion beam etching, and reactive ion etching. A single RIE chemistry was effective in etching both dielectrics as well as delineating the other phases present.

Freescale Semiconductor is employing a new, multi-layer integrated seal (IS) on its next generation accelerometers. The IS, which encloses the moveable sensing element, consists of alternating layers of poly-Si and PSG. A technique needed to be developed to remove the integrated seal in order to permit failure analysis. Mechanical methods were attempted first, but these resulted in severe damage to the sensing element. Chemical deprocessing was considered, but eventually abandoned because there seemed to be no way to protect the sensing elements from the wet etchants that would be used on the IS. Eventually, Reactive Ion Etching (RIE) with an Inductively Coupled Plasma (ICP) source proved to be a successful means for removing the IS without impacting the sensing element. As the design of the integrated seal underwent multiple redesigns, the removal process was successfully modified multiple times to comply with these changes. By using the right gases in the correct order, a high level of selectivity was maintained, allowing for removal of successive layers of different materials (poly-Si, PSG) without harming the sensing element. After removal of some IS designs, a wispy residue was observed on the sensing element and remaining IS support pillars. Chemical analysis identified this material as a by-product of the RIE process, and methods were devised to eliminate it.

DuPont EKC265 Post Etch Residue Remover has been available for many years as post reactive ion etch photo-resist etchant for semiconductor wafer processing. It has also proven useful for the physical analysis of failing semiconductor devices. This paper shows how EKC265 can be used as copper metallization wet etchant to aid in the physical deprocessing. It provides the EKC265 copper metallization etch results and physical deprocessing results using EKC265. An ancillary effect of wet etching copper metallization rather than removing by means of mechanical polishing is that only the thin layer of underlying barrier metal layer has to be removed by means of mechanical polishing. As the barrier metal is a metal-silicon nitride compound, the polishing rate to remove it is close to that of the surrounding oxide. Therefore, less total polishing time is required to remove the copper metallization layer when EKC is used.

The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

In this paper, Failure Analysis (FA) challenges, reliability issues, and new failure modes for copper technology will be presented. Deprocessing techniques for copper technology have been developed and will be discussed. Front side and backside FA deprocessing techniques for copper layers and low k inter-level dielectric (ILD) layers including: reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and a combination of these techniques will be discussed. In addition, novel gate level deprocessing techniques will be presented.

Standard analytical practice in the semiconductor industry depends on fast, efficient and reliable sample preparation prior to FESEM. “In lens” imaging technology and orientation mapping (EBSD) demand sample surfaces free of physical damage and residual contamination. An integrated preparation tool has been developed that incorporates the functionality necessary for argon – oxygen plasma cleaning, ion beam etching (IBE), reactive ion beam etching (RIBE), reactive ion etching (RIE), and ion beam sputter coating (IBSC). Control, monitoring and sequential automation of the processes is accomplished through a novel combination of software and hardware. FESEM results for Al and Cu based microelectronic materials will be discussed, as well as EBSD results for bulk metals. Improvements in throughput and subsequent materials characterization will be demonstrated.

Current methods used for package level destructive physical analysis (DPA) such as chemical and mechanical decapsulation methods, reactive ion etching (RIE) and diamond saw x-section methods could potentially result in artifacts such as die cracking, delamination or corrosion when used on complex packaging technologies such as multiple thin die stacked packages with combination of flip chip and wire bond interconnections. Many of the shortcoming of these ubiquitous DPA tools are being addressed by a laser milling approach to DPA. The system described in this paper consists of a ultraviolet (UV) laser used for local micromachining or milling to access package internal features and a near infrared(IR) laser used for precise soldering of fine wires to enable testing and fault isolation. Applications of the laser milling tool described in the paper are 1) Delayering of multilayer printed circuit board (PCB) substrates to expose internal metal traces so that they can be tested to fault isolate the failure without loosing electrical functionality of the product. 2) Silicon milling to expose flip chip interconnections. 3) Package cross sectioning and 4) Plastic package decapsulation.

With technology scaling down to sub 0.16um and metalization exceeding 7 levels, the development of reproducible backside silicon sample preparation techniques becomes increasingly important to accurately localize defects. Bulk silicon thinning is a critical step in the backside sample preparation process. This paper will discuss two different ways for silicon thinning: reactive ion etching (RIE) alone, and RIE in conjunction with mechanical milling. In addition, the characterization and optimization of the RIE process for backside silicon thinning will be discussed in this paper. We have found mechanical milling works well for many package types; however, we have had difficulty reproducibly thinning certain package types such as very small die or packages where the wire bonds are in the plane of the silicon die and are in very close proximity to the edge of the die. In these cases, we have found that reactive ion etching (RIE) can be used successfully. We have also found that for package types where mechanical milling works, the combination of mechanical milling and reactive ion etching process is a useful technique for accurately controlling the final thickness of the silicon. This technique combines the speed of mechanically milling and the advantage of RIE process to accurately control the etch rate and etch process in the final stages of thinning the silicon die.

In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

A 0.8 μm technology based Electrical Erasable, Programmable Read-Only Memory (EEPROM) cell having a high voltage select transistor and a floating gate transistor with a control gate on top as used in the Motorola Neuron product chip set was analyzed for program and erase failure. Silicon pitting in the select transistor channel was identified to be the failure mechanism. The silicon pitting was experimentally confirmed to be attributed to the penetration of the bottom oxide in the oxide-nitride-oxide (ONO) structure due to the nitride removal using reactive ion etching (RIE). A modified process flow with a thicker sacrificial oxide under the nitride eliminated the pitting failure mechanism and enhanced yield and reliability.