This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

In the failure analysis (FA) of an organic light emitting diode (OLED) display device, fault isolation and physical failure analysis (PFA) were used to identify the root cause of display failure. It is challenging to conduct the FA of a display device, as it consists of display panel, a circuit board and components like semiconductor chips and this integration makes the failure complicated and difficult to analyze and understand. In the case of the display failure studied in this paper, the first work of fault isolation did not clearly identify the origin of the malfunction and its PFA didn’t show any specific defects. To precisely identify the defect location before destructive analysis, the fault isolation technique of OBIRCH was applied to the display device and subsequent PFA successfully identified a crack defect causing the display failure. This finding was given as feedback to the wafer fab and processing parameters were adjusted to prevent generation of the defect in the OLED display device.

In this work we have investigated the results obtained using fault isolation techniques such as EMMI, OBIRCH and OBIC on a Wide band gap power device and in particular a 4H-SiC. We used YLF laser and Green Laser and showed the differences in the resulting hot spots. In the selected point, FIB cross sectioning and EDS analysis was performed. Once that the defect was shown, the differences the fault isolation results were discussed.

Thermal Laser Stimulation (TLS) is employed extensively in semiconductor device fault isolation techniques such as TIVA (Thermal Induced Voltage Alteration), OBIRCH (Optical Beam Induced Resistance Change), SDL (Soft Defect localization), CPA (Critical Parameter Analysis), LADA (Laser Assisted Device Alteration), and LVI (Laser Voltage Imaging), etc. To investigate the TLS effects on 7nm FinFET transistor parameters, several transistors of 7nm FinFET inline ET (Electrical Test) macros were tested while employing TLS of various energy values. The test was done in linear mode so that the joule heating caused by the electrical current would be minimized. The experimental results showed that both NFETs and PFETs experienced increased Ioff (Off current) and Sub_Vt_lin_slope (Subthreshold slope), and decreased Ion (On current) and Vt_lin (Threshold voltage) due to elevated temperature of the transistor from TLS. Higher laser power caused greater effects on transistor parameters. The temperature increase on a transistor by TLS depends on the amount of laser energy transferred to, absorbed by, and dispersed by the transistor area. Factors such as the efficient coupling of the SIL (Solid Immersion Lens) with the Silicon backside surface, the transistor size, and the local layout around the transistor will greatly affect the amount of heat delivered to a particular transistor, even while using the same laser power. Thus, setting the laser power for fault isolation with TLS should consider these factors. Our experimental results also showed that the alteration of transistor parameters under TLS was not permanent if the laser power was carefully selected. It should be noticed that during dynamic fault isolation, a transistor may be switching between off, linear mode, and/or saturation mode. The temperature increase on the transistor under TLS may be higher than anticipated due to joule heating if the transistor operation is not confined to the linear region only. Experiments on transistors operating in saturation mode under TLS can be the subject of future work. The results obtained from these experiments can still establish guidelines for laser power settings to be used in the related fault isolation techniques for devices manufactured at the 7nm node so as to achieve non-destructive fault isolation.

Failure analysis engineers apply a combination of conventional static fault isolation tools such as OBIRCH, PEM, or lock-in thermography (LIT) to detect simple short defects. However, if the defect is located in a complex circuit, analysis can be more challenging. Laser voltage probing and imaging (LVx) is widely used but will have difficulty in localizing a defect in the backend layers. The combination of LVx and LIT can resolve complex short cases that either of these techniques alone cannot easily do. This paper introduces the thermal effect of LVx and applications of LIT for functional analysis, and it describes and provides case histories for complementary fault isolation procedures for detecting defects in metal layers and transistors.

Vertical-cavity surface-emitting lasers (VCSELs) have many advantages over edge-emitting devices, but they tend to be more sensitive to increasing current density both in lifetime and reliability. To better understand this relationship, the authors investigated the cause of 35 failures involving GaAs-based oxide-confined VCSELs. This paper presents a summary of the procedures, methods, and equipment used, the defects and damages observed, and the root causes behind each failure. The authors followed a standard failure analysis workflow consisting of PEM and OBIRCH fault isolation, plan view TEM to confirm the location and distribution of defects, and cross-sectional TEM (XTEM) to determine the profile of a defect at a specific site. All failures examined could be attributed to one of four basic failure mechanisms: burnout due to ESD, dislocations, oxide diffusion, and oxide delamination.

Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers electron beam absorbed current (EBAC), electron beam induced current (EBIC), passive voltage contrast (PVC), optical and electron beam induced resistance change methods (OBIRCH and EBIRCH), lock-in thermography, photon emission microscopy (PEM), and nanoprobing. It describes how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

In this work, two analysis methods for word line (WL) defect localization in NAND flash memory array are presented. One is to use the Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH) to analyze the device through backside, which has no risk of damage during sample preparation. Depending on the I-V characteristics of defects, different analysis tools can be applied. The second method is to analyze a device defect location that is hard to detect through backside analysis. The precise defect site can be localized by Electron Beam Induce Resistance Change (EBIRCH) [1,2], and the defect profile can be observed. The large memory array in NAND flash structure leads to the wide sample movement during EBIRCH analysis. The sub-stage movement function used successfully solves this problem.

The paper demonstrates accurate fault isolation information of metal-insulator-metal (MiM) capacitor failures by lock-in thermograph (LIT). In this study, a phase image spot location at a lock-in frequency larger than 5 Hz gives more accurate defect localization than an LIT amplitude image or OBIRCH to determine the next FA steps.

This research summarizes a variety of physical failure modes of GaAs-based oxide-confined VCSELs and their root causes. Standard failure analysis procedure, which includes defect fault isolation by PEM or IR-OBIRCH and physical inspection by TEM analysis are also presented in detail.

OBIRCh(Optical Beam Induced Resistance Change) and TIVA (Thermal Induced Voltage Alteration) are widely used ElectricalFailure Analysis techniques for finding defects under static conditions. This paper will discuss the requirements for a good amplifier to be used for OBIRCh, and recent improvements that have been released to market from Thermo Fisher Scientific.

We report and demonstrate a new methodology for the localization of dielectric breakdown sites in through-silicon via (TSV) structures. We apply a combination of optical beam induced resistance change (OBIRCH) and mechanical/chemical chip deprocessing techniques to localize nm-sized pinhole breakdown sites in a high aspect ratio 3x50 ìm TSV array. Thanks to the wavelength-selective absorption process in silicon, we can extract valuable defect depth localization info from our laser stimulation measurement. After chip deprocessing we inspect and localize the defect site in the dielectric liner using a scanning electron microscope (SEM). We confirm our results and analysis by cross-sectioning a TSV with a focused-ion beam (FIB).

Massively parallel test structures, based on looking for shorts between certain design elements in the SRAM cells, are becoming increasingly relied upon in yield characterization. The localization of electrical shorts in these structures has posed significant challenges in advanced technology nodes, due to the size, and design complexity. Several of the traditional methods (nanoprobing, OBIRCH, etc.) are shown to be inadequate to find defects in SRAM cells, either due to resolution, or time required. In recent years, the Electron Beam Induced Resistance Change (EBIRCH) technique has increasingly been utilized for failure analysis. Combining EBIRCH with other techniques, such as SEM based nanoprobing system and PVC, allows not only direct electrical characterization of suspicious bridging sites but also allows engineers to pinpoint the exact location of defects with SEM resolution. This paper will demonstrate the several cases where SRAM-like test structures provided extreme challenges, and EBIRCH was the key technique towards finding the fail. A node to node, node to wordline, and ground-ground contact fails are presented. A combination of EBIRCH with the more traditional techniques in advanced technology node is key to timely and accurate determination of shorting mechanisms in our test structures.

Electron-Beam Induced Resistance CHange (EBIRCH) is a technique that makes use of the electron beam of a scanning electron microscope for defect localization. The beam has an effect on the sample, and the resistance changes resulting from that effect are mapped in the system. This paper explores the beam-based nature of the technique and uses understanding from another beam-based technique, Optical Beam Induced Resistance CHange (OBIRCH), to propose a dominant mechanism. This mechanism may explain the widely different success rates between different types of samples observed after six month’s use of the technique for isolations on large health of line structures in a failure analysis lab.

Optical beam induced resistance change (OBIRCH) is a very well-adapted technique for static fault isolation in the semiconductor industry. Novel low current OBIRCH amplifier is used to facilitate safe test condition requirements for advanced nodes. This paper shows the differences between the earlier and novel generation OBIRCH amplifiers. Ring oscillator high standby leakage samples are analyzed using the novel generation amplifier. High signal to noise ratio at applied low bias and current levels on device under test are shown on various samples. Further, a metric to demonstrate the SNR to device performance is also discussed. OBIRCH analysis is performed on all the three samples for nanoprobing of, and physical characterization on, the leakage. The resulting spots were calibrated and classified. It is noted that the calibration metric can be successfully used for the first time to estimate the relative threshold voltage of individual transistors in advanced process nodes.

Low power mode current is a very important parameter of most microcontrollers. A non-production prototype microcontroller had high current issues with certain SRAM modules which were produced using a new memory compiler. All devices were measuring 100’s μA of low power mode current which was an order of magnitude higher than the requirement. Many failure analysis (FA) techniques had to be used to determine the root cause: Optical Beam Induced Resistance Change (OBIRCh), photo emission microscopy (PEM), microprobing, and nanoprobe device characterization. Transistor models and measurements of probe structures from the effected lots both predicted that the device low power mode current would meet expectations; however, all first silicon samples had elevated low power mode current. A knowledge of low power design methodology was needed to ensure all issues were discovered.

OBIRCH is a static technique for isolating both high and low resistance failures in test structures that continues to be relevant to sub 14nm technologies. While limited resolution is a factor as devices get smaller, an approximate location is adequate for finding obvious defects on sub 14nm technology structures. Its speed is what makes this technique appealing. If the approximate location isn’t good enough, a more time-consuming, higher-resolution technique can be employed. But the use of OBIRCH as a first isolation technique saves considerable time for a high volume FA lab if obvious defects cause the majority of failures. The seven case studies on sub 14nm technology are examples of obvious defects where OBIRCH had adequate resolution for isolation. The OBIRCH results for the first example are compared to the PVC (Passive Voltage Contrast) and EBAC (Electron-Beam Absorbed Current Imaging) findings to illustrate each technique’s strength and weakness.

The timely and accurate imaging of problems in p/n junctions is increasingly important. Scanning Capacitance Microscopy is a current standard for precise 2D-mapping of carrier profiles, but care must be taken to choose the correct field of view because of the slow scan time. This paper provides commentary on the usefulness and possible pitfalls of a wide range of techniques available to the modern FA analyst, with examples from problem solving in a process development environment. SEM passive voltage contrast may provide imaging of junctions, but may be limited to N-well / P-well after special sample prep. OBIRCH provides reliable information on any current flows, but may not be selective specifically to those involving junction problems. Electron Beam Induced Current provides junction information at SEM resolution, but it may be hard for subtle problems to not be swamped out by massive signals. Multi-photon OBIC shows promise for high-resolution laser-based imaging, but may require highly special wiring. Photon Emission is an old standby. A case study is given which shows that one must be careful to match camera type and defect mechanism type in order to be able to see actual junction leakage.