In prior work, it was demonstrated that information about device turn-on can be obtained in a nanoprobing setup which involves no applied bias across the channel. This was performed on nFET logic devices in 7 nm technology and attributed to the Seebeck effect, or heating from the SEM beam. In this work, the experiments are continued to both nFET and pFET devices and on both 22 nm and 5 nm devices. Further discussion about the opportunities and evidence for Seebeck effect in nanoprobing are discussed.

As advanced device technologies scale to 5nm with dimensions getting smaller and materials change, it is difficult to control the sample preparation delayering end pointing by polishing. Therefore, it requires an alternative solution such as Xe+ PFIB (Plasma Focused Ion beam) Microscopy for accurate delayering control. PFIB can be used for planar Failure Analysis (FA) delayering but also for nanoprobing sample preparation. This paper introduces the detail of nanoprobing sample preparation by PFIB and discusses nanoprobing results on 5nm FinFET technology.

Delayering is an essential sample preparation step in physical failure analysis (PFA) of integrated circuits (IC). During delayering it is crucial to precisely control the endpoint and uniformity of the region of interest (ROI). Furthermore, to perform SEM based nanoprobing it is also required to end the delayering process without residues on the surface that will reduce conductivity of, or induce shorts between, isolated contacts. Delayering via mechanical polishing has been the main approach for PFA and nanoprobing. However, as the shrinkage of the interconnect layer thickness reduced below 100 nm, it has become very challenging to control the polish endpoint and to achieve robustly controlled process. Recently gas assisted Xe+ Plasma FIB (PFIB) has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. The purpose of this study is to analyze the PFIB ion beam interaction with MOSFET devices, addressing ion beam damage related device degradation. We explored the final surface treatment required for nanoprobing and the impact on MOSFETs. For this purpose, we monitored device parameters after PFIB delayering final steps with different beam conditions and compare PFIB prepared samples to polished prepared samples. Consequently, we summarize the considerations of parameters for ion beam on final surface treatment.

Electrostatic discharge (ESD) can easily damage the nanoprobes used in the failure analysis of semiconductor devices. Nanoprobes with tips that have radii of curvature of a few nanometers are especially sensitive to ESD damage, because applying even modest electrical potentials leads to high electrical fields at the tip of the sharp probe. ESD damage has been used as an umbrella explanation to explain a variety of probe failures and undesirable tip features, but due to the stochastic nature of these events, its effect on nanoprobes has hitherto not been well documented. This paper describes the effect that ESD events have on the tip profile of nanoprobes and describes best practices so that such events can be more readily diagnosed and prevented by nanoprobe users. The likelihood of an ESD event occurring can be reduced by eliminating potential differences between users and the probes and by regulating laboratory humidity levels.

This presentation provides an overview of nanoprobe systems and what they reveal about defects and abnormalities in semiconductor device structures and materials. The presentation covers the basic operating principles, implementation, and capabilities of atomic force probe and beam-based imaging techniques, including AFP pico-current contrast and scanning capacitance imaging, SEM/FIB active voltage contrast imaging, and SEM/FIB electron-beam absorbed current (EBAC), induced current (EBIC), and induced resistance change (EBIRCH) imaging. It also includes guidelines for probing transistors and copper metallization and case studies in which nanoprobing was used to analyze gate oxide and substrate defects, intermittent bit cell failures, threshold voltage shifts, and time-domain popcorn noise.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers passive voltage contrast (PVC), nanoprobing, conductive atomic force microscopy, and photon emission microscopy (PEM). It describes signal types, how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

This paper presents the results of an investigation to gain a better understanding of the impact of wafer substrate copper (Cu) contamination on FinFET devices. A chip from a wafer free of Cu contamination and several chips near a Cu contaminated wafer edge were sampled for chemical, structural, and morphological analysis and electrical device performance testing. The contaminated wafer was also annealed at high temperature, trying to drive Cu diffusion further into the Si substrate. TEM analysis revealed that the Cu interacted with Si to form a stable η-Cu 3 Si intermetallic compound. SIMS analysis from the backside of the wafer detected no Cu even after most of the backside material was removed. Likewise, electrical nanoprobing showed no parametric drift in the FinFETs near the edge of the wafer, comparable to device behavior in a Cu-free Si substrate. These results indicate that the formation of η-Cu 3 Si with a well-defined crystalline structure and stable stoichiometry immobilizes Cu diffusion in the Si substrate. In other words, the impact of Cu diffusion in silicon has no effect on device performance as long as η-Cu 3 Si does not form in the FinFET channel or short any structures within the chip.

This paper explains how nanoprobe analysis was used to determine the cause of data retention failures in nonvolatile memory (NVM) bitcells. The challenge with such memory cells is that they consist of two transistors with a single control gate in series with a programmable floating gate connected by a shared source/drain active area. With such a layout, there is no way to isolate the control gate from the floating gate, meaning that characterization must be performed simultaneously on both transistors. Having to characterize two transistors connected in series increases the number of potential electrical signature effects not by a factor of two, but rather the power of two, which makes interpreting the results much more difficult. As discussed in the paper, however, the authors used an atomic force probe to verify the bit map of the faulty device and then analyze the failing bit to confirm the programming error and reveal the possible failure mechanism. The failure mechanism was determined based on its electrical signature and a physical analysis of the bitcell location.

In this paper, we describe the difference between oscilloscope pulsing tests and waveform generator fast measurement unit (WGFMU) tests in analyzing high-resistance defects in DRAM main cells. Nanoprobe systems have various constraints in terms of pulsing whether it involves an oscilloscope or pulse generator. There are certain types of devices, such as DRAM cells, for which these systems are ineffective because saturation currents are too small. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in combination with an electro-optical nanoprobe.

This presentation provides an overview of nanoprobe systems and what they reveal about defects and abnormalities in semiconductor device structures and materials. The presentation covers the basic operating principles, implementation, and capabilities of atomic force probe and beam-based imaging techniques, including AFP pico-current contrast and scanning capacitance imaging, SEM/FIB active voltage contrast imaging, and SEM/FIB electron-beam absorbed current (EBAC), induced current (EBIC), and induced resistance change (EBIRCH) imaging. It also includes guidelines for probing transistors and copper metallization and case studies in which nanoprobing was used to analyze gate oxide and substrate defects, intermittent bit cell failures, threshold voltage shifts, and time-domain popcorn noise.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers electron beam absorbed current (EBAC), electron beam induced current (EBIC), passive voltage contrast (PVC), optical and electron beam induced resistance change methods (OBIRCH and EBIRCH), lock-in thermography, photon emission microscopy (PEM), and nanoprobing. It describes how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

In order to understand and communicate a PFA strategy during an analysis, a two-dimensional diagram of the layout of a suspect net has been developed. Net connections are extracted from the layout and drawn in a two-dimensional stitch diagram. The result is a simplified diagram providing a stack view of the layout layers for the net(s) of interest. Key analysis decisions are made and communicated using the stitch diagram. Using this diagram, selective nanoprobe measurements are made. Software implementation that extracts and draws the diagram allows for faster creation as well as making larger nets practical. As examples show, nanoprobe curve trace analysis using a simplified diagram has proven to be a successful evidence based approach to physical failure analysis of complex nets.

For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.

The global radio frequency (RF) semiconductor market size is growing dramatically in recent years, especially with the growing demand for mobile devices, communication networks, automotive applications, etc. Failure analysis (FA) on RF devices is normally more complex than digital devices, especially when it involves soft failure. This paper discusses FA on an RF product soft failure issue by the pulsed currentvoltage (IV) nanoprobing technique. The device suffered from high-frequency failure and exhibited abnormal repetitive softstart signature. Previous publications on pulsed IV nanoprobing applications were mostly related to Front End Of Line (FEOL) issues and simulations. In most of these cases, the electrical abnormality could also be observed with normal DC IV measurement. In this paper, the pulsed IV nanoprobing was performed at the Back End Of Line (BEOL) interconnects to isolate the failure that was otherwise not detected with normal DC nanoprobing or the reported pulse IV measurement. The proposed method successfully isolate, simulate the failure, and helping us to identify the process and design rule weakness.

This paper demonstrates a methodology for chip level defect localization that allows complex logic nets to be approached from multiple perspectives during failure analysis of modern flip-chip CMOS IC devices. By combining chip backside deprocessing with site-specific plasma Focused Ion Beam (pFIB) low angle milling, the area of interest in a failure IC device is made accessible from any direction for nanoprobing and Electron Beam Absorbed Current (EBAC) analysis. This methodology allows subtle defects to be more accurately localized and analyzed for thorough root-cause understanding.

Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.

Non-volatile memory is the most important memory device in IC chips. As a memory, embedded non-volatile memory (NVM) is a fundamental structure in many kinds of semiconductor devices. It is commonly used in the modern electrical appliance as a code or data memory. For different applications, there are different memory designs or IP, like ROM, OTP, Flash, MRAM, PCRAM etc. The physical mechanism of these NVMs are different, some are electron based, some are resistance based and fuse or anti-fused based. The experiment described in this paper is performed on an electron charge storage based NVM. That means a medium is employed to store electron charge to differentiate two statuses “0” and “1”. Floating Poly gate is this medium used as electron charge storage in this NVM. Since the storage medium is in floating condition, it cannot be accessed externally. The methods of performing direct analysis are limited for this kind of device, especially in the case of subtle defects or soft fail. As semiconductor devices scale, the defects become smaller and more subtle. Nanoprobing is usually the only way to find the defect location electrically before any further physical analysis. In this experiment, the single bit NVM fail was analyzed. Different PFA methods used during the analysis, failed to find the defect. Nanoprobing was employed to precisely isolate the defect. Key word: nanoprobing, NVM, subtle defect, Poly-crystalline, floating gate