This study shows that a high-volume TEM workflow can be achieved for inline defect characterization by adding a defect marking step using commercially available tools. A simple user-assisted defect marking procedure added to a conventional automated ex-situ lift-out TEM workflow increased throughput by a factor of nearly three and reduced man-hours by an order of magnitude, a significant improvement over conventional TEM workflows.

Fast and accurate examination from the bulk to the specific area of the defect in advanced semiconductor devices is critical in failure analysis. This work presents the use of Ar ion milling methods in combination with Ga focused ion beam (FIB) milling as a cutting-edge sample preparation technique from the bulk to specific areas by FIB lift-out without sample-preparation-induced artifacts. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 15 nm are obtained.

A protocol for obtaining an advanced TEM lamella geometry using FIB-SEM is presented. Lamella lift-out procedure might require multiple manipulation steps or even breaking the vacuum in order to reach inverted or plan-view lamella geometries. We have developed a setup which enables lamella transfer from a bulk sample onto a TEM grid within a single, very simple manipulation step, with no need to break the vacuum or unload the sample. Most importantly, this approach does not require any additional devices to be installed.

Protection layers on double ex situ lift-out TEM specimens were investigate in this paper and two protection layer approaches for double INLO or double EXLO were introduced. The improved protection methods greatly decreased the damage layer on the top surface from 90 nm to 5 nm (or lower) during FIB milling. According to the property of different sample and its preliminary treatment in the FIB, we have the satisfactory approaches to be applied. Using this improved protection method, we demonstrate the structures within the TEM lamella can be observed without ion beam damage/implantation during FIB

As the new generation of microelectronics is pushed into smaller spaces and the yield production is pushing to lower the unoccupied spaces on chips, the local variation of stress has an influence on the component’s performance. This stress comes mainly from different thermal and mechanical properties of the materials used especially in 3D integrations like through silicon via (TSV) technology [1]. Through finite element simulation [2] the internal strain profile was modelled and based on these findings we devised a simulation model for a large area chunk lift out, to preserve the stress inside the material. Standard preparation method for strain measurement is to use a wafer dicing saw and subsequently focused ion beam (FIB) milling, to create lamellae with a defined geometry, close to the desired TSV. This method requires different equipment and knowledge base to achieve a lamella which is still contaminated by Gallium. Therefor we developed our own method based on an FE model of a large chunk lift out, where only a Xenon Plasma FIB is utilized until the local stress measurement using convergent beam electron diffraction (CBED) is measured in a transmission electron microscope (TEM).

Practice and training samples have been manufactured using 3D-printing methods. These 3D-printed samples mimic the exact geometry of focused ion beam (FIB) prepared specimens and can be used to help master ex situ and in situ lift out micromanipulation methods. An additively manufactured array of samples yields numerous samples needed for repetition and deliberate practice necessary to master the lift out and micromanipulation steps. The 3D-printed samples are cost effective and negates expensive FIB time needed to prepare FIB specimens.

Low energy (i.e., 5 keV, 3 keV) Xe+ plasma FIB methods were applied to Si ex situ lift out specimens. Cs-corrected STEM imaging reveals the Si dumbbell structure indicating excellent surface quality achieved during the low energy polishing steps.

Vacuum assisted ex situ lift out may be used for fast, easy, and reproducible plan view specimen preparation. Manipulation of samples via beveled hollow glass probes whose plane of interest is parallel to slotted grids allow for conventional FIB milling for S/TEM analysis.

The semiconductor industry recently has been investigating new specimen preparation methods that can improve throughput while maintaining quality. The result has been a combination of focused ion beam (FIB) preparation and ex situ lift-out (EXLO) techniques. Unfortunately, the carbon support on the EXLO grid presents problems if the lamella needs to be thinned once it is on the grid. In this paper, we show how low-energy (< 1 keV), narrow-beam (< 1 μm diameter) Ar ion milling can be used to thin specimens and remove gallium from EXLO FIB specimens mounted on various support grids.

The semiconductor industry is constantly investigating new methods that can improve both the quality of TEM lamella and the speed at which they can be created. To improve throughput, a combination of FIB-based preparation and ex situ lift-out (EXLO) techniques have been used. Unfortunately, the carbon support on the EXLO grid presents problems if the lamella needs to be thinned once it is on the grid. In this paper, we present low-energy (<1 keV), narrow-beam (<1 μm diameter), Ar+ ion milling as a method of preparing electron-transparent and gallium-free EXLO FIB specimens.

Device failure analysis typically requires multiple systems for fault identification, preparation and analysis. In this paper we discuss the practicalities and limits of using a single FIBSEM system for a complete failure analysis workflow. The theoretical requirements of using a nanomanipulator for both lamella lift out and electrical testing are discussed and the current capabilities of windowless X-rays detectors for chemical analysis demonstrated. When the required resolution for failure analysis exceed the limits of a FIBSEM and TEM is required, the combination of the nanomanipulator and X-ray detector for advanced lift out and thickness controlled thinning techniques are demonstrated to prepare exceptional quality lamellae.

Ex situ lift out is fast, easy, and reproducible, and adds flexibility for either frontside or backside manipulation of focused ion beam milled specimens. ex situ lift out methods may be enhanced by eliminating electrostatic forces. In addition, optimizing the geometry of the specimen relative to the probe improves the Van der Waals forces responsible for the lift out and subsequent manipulation of focused ion beam prepared specimens.

When failure analysis is performed on a circuit composed of FinFETs, the degree of defect isolation, in some cases, requires isolation to the fin level inside the problematic FinFET for complete understanding of root cause. This work shows successful application of electron beam alteration of current flow combined with nanoprobing for precise isolation of a defect down to fin level. To understand the mechanism of the leakage, transmission electron microscopy (TEM) slice was made along the leaky drain contact (perpendicular to fin direction) by focused ion beam thinning and lift-out. TEM image shows contact and fin. Stacking fault was found in the body of the silicon fin highlighted by the technique described in this paper.

Ex situ lift out (EXLO) is performed outside of the FIB instrument on a system basically consisting of a light optical microscope, stage, and manipulator. EXLO may be used to lift out very large specimens prepared using plasma FIB instruments. This paper combines a vacuum micropipetting module with an EXLO station, making use of both suction vacuum forces and adhesion forces for the pick and place of a FIB milled free specimen onto a slotted EXpressLO grid. The geometry for manipulation to EXpressLO grids is detailed in this paper. It is observed that the vacuum assisted lift out optimizes specimen positioning for easy placement on the novel EXpressLO grid. Once on the new grid, an electron transparent specimen may be analyzed directly by S/TEM or other analytical techniques. The specimen on this grid can also be further FIB milled or processed prior to analysis.

Electron Beam Induced Current (EBIC) characterization is unique in its ability to provide quantitative high-resolution imaging of electrical defects in solar cells. In particular, EBIC makes it possible to image electrical activity of single dislocations in a Dual-Beam Focused Ion Beam (FIB) Scanning Electron Microscope (SEM), to cut and lift out a micro-specimen containing a particular dislocation, and then transfer it for further structural or chemical analysis. As typical solar cell material presents a complex array of defects, it is important to observe statistical variations within a sample and select key sites for analysis. This paper describes a method for automated defect identification and characterization, and shows an application to multi-crystalline silicon (mc-Si) solar cell wafers selected from different heights along the manufactured ingot. Information presented here includes the experimental setup for data acquisition, as well as the basic algorithms used for identification and extraction of dislocation contrast.

A Plasma-source focused ion beam (Helios PFIB) DualBeam™ microscope with sub-nanometer 1kV SEM resolution was used to investigate the structure of a state-of-the-art organic light-emitting diode (OLED) display. The capability of the Helios PFIB to produce and manipulate millimeter-scale samples for wide field-of-view crosssectional SEM analyses was demonstrated by lifting out a 570μm long by 40μm wide x 10μm deep and mounting it on a copper half-grid. An angled face was cut into the chunk and high-resolution back-scattered SEM tiles across the entire exposed face were automatically acquired within a modular automated processing system (MAPS).

Ex situ lift out (EXLO) was historically the first lift out technique to be developed for site specific removal and manipulation of focused ion beam (FIB)-prepared specimens to a suitable carrier. In this paper, fast plasma FIB (PFIB) preparation of large scanning/transmission electron microscope specimens is combined with fast conventional EXLO and EXpressLO "pick and place" solutions. The combination of large material removal rates with PFIB and EXLO allows for efficiency and high throughput of FIB lift out specimens.

Several methods are used to invert samples 180 deg in a dual beam focused ion beam (FIB) system for backside milling by a specific in-situ lift out system or stages. However, most of those methods occupied too much time on FIB systems or requires a specific in-situ lift out system. This paper provides a novel transmission electron microscopy (TEM) sample preparation method to eliminate the curtain effect completely by a combination of backside milling and sample dicing with low cost and less FIB time. The procedures of the TEM pre-thinned sample preparation method using a combination of sample dicing and backside milling are described step by step. From the analysis results, the method has applied successfully to eliminate the curtain effect of dual beam FIB TEM samples for both random and site specific addresses.

With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.