Modern processors rely heavily on memory arrays close to the logical processers to have minimal latencies and highest bandwidth for optimal performance. There are memory arrays in the client and server which are configured to different levels based on the size and latency required for the tasks. These memory arrays are separated into bit lines and word lines to address single bits and retrieve required data from the address of the memory location. In any new server validation, a memory access error can happen if the logical to physical memory address is not confirmed. This can lead to corrupt data and operation failure. We have employed here, novel targeted Focused Ion Beam (FIB) milling techniques for Logical to Physical (L2P) memory addressing validation and correction.

Passive voltage contrast (PVC) is a well-known fault isolation technique in differentiating contrast at via/metal/contact levels while focused ion beam (FIB) is a destructive technique specifically used for cross sectioning once a defect is identified. In this study, we highlight a combination technique of PVC and progressive FIB milling on advanced node fin field-effect transistor (FinFET) for root cause analysis. This combo technique is useful when applied on high-density static random access memory (SRAM) structure, especially when it is difficult to view the defect from top-down inspection. In this paper, we create a FA flow chart and FIB deposition/milling recipe for SRAM failure and successfully apply them to three case studies.

Fast and accurate examination from the bulk to the specific area of the defect in advanced semiconductor devices is critical in failure analysis. This work presents the use of Ar ion milling methods in combination with Ga focused ion beam (FIB) milling as a cutting-edge sample preparation technique from the bulk to specific areas by FIB lift-out without sample-preparation-induced artifacts. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 15 nm are obtained.

An advanced technique for site-specific Atom Probe Tomography (APT) is presented. An APT sample is prepared from a targeted semiconductor device (commercially available product based on 14nm finFET technology). Using orthogonal views of the sample in STEM while FIB milling, a viable APT sample is created with the tip of the sample positioned over the lightly-doped drain (LDD) region of a pre-defined PFET. The resulting APT sample has optimal geometry and minimal amorphization damage.

Protection layers on double ex situ lift-out TEM specimens were investigate in this paper and two protection layer approaches for double INLO or double EXLO were introduced. The improved protection methods greatly decreased the damage layer on the top surface from 90 nm to 5 nm (or lower) during FIB milling. According to the property of different sample and its preliminary treatment in the FIB, we have the satisfactory approaches to be applied. Using this improved protection method, we demonstrate the structures within the TEM lamella can be observed without ion beam damage/implantation during FIB

As the new generation of microelectronics is pushed into smaller spaces and the yield production is pushing to lower the unoccupied spaces on chips, the local variation of stress has an influence on the component’s performance. This stress comes mainly from different thermal and mechanical properties of the materials used especially in 3D integrations like through silicon via (TSV) technology [1]. Through finite element simulation [2] the internal strain profile was modelled and based on these findings we devised a simulation model for a large area chunk lift out, to preserve the stress inside the material. Standard preparation method for strain measurement is to use a wafer dicing saw and subsequently focused ion beam (FIB) milling, to create lamellae with a defined geometry, close to the desired TSV. This method requires different equipment and knowledge base to achieve a lamella which is still contaminated by Gallium. Therefor we developed our own method based on an FE model of a large chunk lift out, where only a Xenon Plasma FIB is utilized until the local stress measurement using convergent beam electron diffraction (CBED) is measured in a transmission electron microscope (TEM).

Dopants imaging using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy are used for identifying doped areas within a device, the latter being analyzed either in a top view or in a side view. This paper presents a sample preparation workflow based on focused ion beam (FIB) use. A discussion is then conducted to assess advantages of the method and factors to monitor vigilantly. Dealing with FIB machining, any sample preparation geometry can be achieved, as it is for transmission electron microscopy (TEM) sample preparation: cross-section, planar, or inverted TEM preparation. This may pave the way to novel SCM imaging opportunities. As FIB milling generates a parasitic gallium implanted layer, a mechanical polishing step is needed to clean the specimen prior to SCM imaging. Efforts can be conducted to reduce the thickness of this layer, by reducing the acceleration voltage of the incident gallium ions, to ease sample cleaning.

The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.

Vacuum assisted ex situ lift out may be used for fast, easy, and reproducible plan view specimen preparation. Manipulation of samples via beveled hollow glass probes whose plane of interest is parallel to slotted grids allow for conventional FIB milling for S/TEM analysis.

In this paper we introduce a physical analysis approach using focus ion beam (FIB) and scanning electron microscopy (SEM) to investigate a micro defective structure at active contact trench which caused a voltage breakdown of power device. In this case study, a lower probe current through FIB milling and a lower accelerating voltage in SEM imaging have been applied to identify the micro structure defect.

An in situ air gaps fill-in approach was investigated by conducting a convenient way in dual-beam FIB. We employed a well-controlled deposition to precisely fill carbon into air gaps. It greatly reduced formation of the artifacts and avoided the profiles of air gaps by reducing striations and damages during FIB milling. Generally, the effect of air gaps between wordlines or between metal lines, as well as some unexpected defect voids can be eliminated in most cases if this ideal method is applied.

An advanced sample preparation protocol using Xe+ Plasma FIB for increasing FA throughput is proposed. We prepared cross-sections of 400 μm and wider in challenging samples such as a BGA (CSP), bond wires in mold compound or a TSV array. These often suffer from FIB milling artifacts. The unsatisfactory quality of the cross-section face is mainly due to extremely different milling rates of the various materials (polyimide, tin, copper, mold compound, platinum), ion beam induced ripples [1] or due to significant surface topography. We explored the usability of the protocol for standard cross-sections and also tested the preparation of TEM lamellae. The process parameters of the proposed approach were compared with the standard methods of Xe+ Plasma FIB FA with respect to preparation time and cross-section quality. Aiming for ultimate results, we incorporated the Rocking stage technique which also greatly improves cross-section quality.

Ex situ lift out (EXLO) is performed outside of the FIB instrument on a system basically consisting of a light optical microscope, stage, and manipulator. EXLO may be used to lift out very large specimens prepared using plasma FIB instruments. This paper combines a vacuum micropipetting module with an EXLO station, making use of both suction vacuum forces and adhesion forces for the pick and place of a FIB milled free specimen onto a slotted EXpressLO grid. The geometry for manipulation to EXpressLO grids is detailed in this paper. It is observed that the vacuum assisted lift out optimizes specimen positioning for easy placement on the novel EXpressLO grid. Once on the new grid, an electron transparent specimen may be analyzed directly by S/TEM or other analytical techniques. The specimen on this grid can also be further FIB milled or processed prior to analysis.

To help solve the navigational problem, i.e., being able to successfully locate a circuit for probing or editing without destroying chip functionality, a near-infrared (NIR), near-ultraviolet (NUV), and visible spectrum camera system was developed that attaches to most focused ion beam (FIB) or scanning electron microscope vacuum chambers. This paper reviews the details of the design and implementation of the NIR/NUV camera system, as instantiated upon the FEI FIB 200, with a particular focus on its use for the visualization of buried structures, and also for non-destructive real time area of interest location and end point detection. It specifically considers the use of the micro-optical camera system for its benefit in assisting with frontside and backside circuit edit, as well as other typical FIB milling activities. The quality of the image obtained by the IR camera rivals or exceeds traditional optical based imaging microscopy techniques.

Cross sections of large Through Silicon Vias (TSV) and solder bumps are often prepared using the Focused Ion Beam (FIB). The high current Xe plasma ion source allows fast and precise target preparation of TSV with small diameter. Solder bumps can be accessed due to the high milling rate too. However, the high current milling by plasma FIB causes the worsening of the milled surface quality. An optimized FIB scanning strategy accompanied with the novel rocking stage for the sample tilting during the milling has been developed for the plasma FIB. Whole milling process is observed by the Scanning Electron Microscopy (SEM). Time to prepare a cross section is accelerated and the excellent quality is suitable for subsequent failure analysis. Also important is proper sample cleaving before FIB milling. Using an accurate method to cleave the sample prior to FIB preparation further reduces the overall sample preparation time. The high quality cross sections prepared using this new method are ready not only for SEM but also for EDX and EBSD analysis, either 2D or 3D, when combined with FIB slicing. Broadening the analysis to these techniques increases the obtainable information, allowing the arrangement of materials and their crystalline structure to be studied in a detail.

With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.

In this paper different sample preparation strategies for fast and efficient failure analysis of 3D devices are reviewed and further explored. It will be shown that a combined workflow using laser ablation and plasma FIB milling provides best flexibility to cover most of the FA use cases. Laser ablation guarantees fast, coarse material removal and the subsequent plasma FIB milling provides fast removal of any damage or imperfections induced by the laser ablation, precise navigation to the region of interest, a high quality surface finish allowing direct SEM imaging and analytics such as EBSD and, if required the preparation of a thin lamella for TEM analysis.

3D tomography of TSVs was performed by combining Xe plasma FIB milling and lift-out techniques. This approach allows analyzing the structure of TSVs in detail using a method faster than the usual 3D tomography by Ga FIB and more precise than X-ray tomography. Both well-filled TSVs and TSVs with voids were analyzed and the results were compared. The analysis procedure was optimized in order to reduce the analysis time and to increase the throughput. The lift-out of the analyzed block of material was performed to obtain 90° angle between TSV and the ion beam axes, which is critical to reduce the curtaining effect and which allowed to increase FIB beam current significantly, reducing the analysis time.

Focused ion beam (FIB) tools for backside circuit edit play a major role in the validation of integrated circuit (IC) design modifications. Process scaling is one of many significant challenges, because it reduces the accessible area to modify transistors and IC interconnects in the design. This paper examines the geometries available for FIB nanomachining, via milling/etching, and deposited metal jumpers by analyzing polygon data from computer aided design (CAD) virtual layers gathered across four process technologies, from 180nm down to 28nm. The results of this analysis demonstrate that the combination of silicon nanomachining box length and FIB via box length identifies the most challenging aspects of the FIB edit. The smallest geometries include a 300 nanometer silicon access area with a FIB milled 200 nanometer via inside it. More advanced technology nodes will require the ability to make smaller geometries without the help of integrated design features typically referred to as design for FIB/Debug.