In this work, we investigate mushroom type phase-change material (PCM) memory cells based on Ge 2 Sb 2 Te 5 . We use low-angle annular dark field (LAADF) STEM imaging and energy dispersive X-ray spectroscopy (EDX) to study changes in microstructure and elemental distributions in the PCM cells before and after SET and RESET conditions. We describe the microscope settings required to reveal the amorphous dome in the RESET state and present an application example involving the failure analysis of a PCM test array made with devices fabricated at IBM’s Albany AI Hardware Research Center.

The continuously growing demands in high-density memories drive the rapid development of advanced memory technologies. In this work, we investigate the HfOx-based resistive switching memory (ReRAM) stack structure at nanoscale by high resolution TEM (HRTEM) and energy dispersive X-ray spectroscopy (EDX) before and after the forming process. Two identical ReRAM devices under different electrical test conditions are investigated. For the ReRAM device tested under a regular voltage bias, material redistribution and better bottom electrode contact are observed. In contrast, for the ReRAM device tested under an opposite voltage bias, different microstructure change occurs. Finite element simulations are performed to study the temperature distributions of the ReRAM cell with filaments formed at various locations relative to the bottom electrode. The applied electric field as well as the thermal heat are the driving forces for the microstructure and chemical modifications of the bottom electrode in ReRAM deceives.

Lock-in thermography (LIT) has been successfully applied in different excitation and analysis modes including classical LIT, analysis of the time-resolved temperature response (TRTR) upon square wave excitation and TRTR analysis in combination with arbitrary waveform stimulation. The results obtained by both classical square wave- and arbitrary waveform stimulation showed excellent agreement. Phase and amplitudes values extracted by classical LIT analysis and by Fourier analysis of the time resolved temperature response also coincided, as expected from the underlying system theory. In addition to a conceptual test vehicle represented by a point-shaped thermal source, two semiconductor packages with actual defects were studied and the obtained results are presented herein. The benefit of multi-parametric imaging for identification of a defect’s lateral position in the presence of multiple hot spots was also demonstrated. For axial localization, the phase shift values have been extracted as a function of frequency [4]. For comparative validation, LIT analyses were conducted in both square wave and arbitrary waveform excitation using custom designed and sample-specific stimulation signals. In both cases result verification was performed employing X-ray, scanning electron microscopy (SEM) and energy dispersive x-ray (EDX) as complementary techniques.

Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

This paper describes the failure analysis methods used to characterize micro cracks that resulted in laser vias of printed circuit boards (PCBs) through case studies of destructive failure analysis. Defects such as cracks in laser vias of PCBs can cause open or low leakage failure mode of module due to improper cleaning during the PCB process, natural oxide films such as brown oxide, or physical forces by use. Therefore, it’s difficult to identify the causes of these phenomena unless proper analytical techniques are used. In this study, multiple analytical techniques are employed to characterize micro cracks in laser vias. The destructive analysis with cross section and ion milling process is used to detect and inspect an accurate micro crack phenomenon of laser via. The characterization analysis using TEM, EDX and SIMS equipment after separating laser vias from a PCB is used to analyze failure cause of micro crack in laser via. This paper will be concluded with a discussion about what physical analysis methods should be used to analyze the causes of micro cracks for laser vias of PCBs.

The State-of-the-Art FinFET technology has been widely adopted in the industry, typically at 14 nm and below technology nodes. As fin dimensions are pushed into the nanometer scale, process complexity is highly escalated, posing great challenges for physical failure analysis. Meanwhile, the accelerated cycles of learning for new technology nodes demand high accuracy and fast turnaround time to solve the material and interface issues pertaining to semiconductor processing or device failure. In this paper, we report a case study of fin related defect that caused device failure. Several analytical techniques, namely, Scanning Electron Microscopy (SEM), plan-view and cross-section Transmission Electron Microscopy (TEM) with Energy Dispersive X-ray spectroscopy (EDX), Electron Energy Loss Spectroscopy (EELS) and Z-contrast tomography were employed to characterize the defect and identify root-cause, leading to the resolution of this issue.

In this paper, the localization of open metal contact for 90nm node SOC is reported based on Electron Beam Absorbed Current (EBAC) technique and scan diagnosis for the first time. According to the detected excess carbon, silicon and oxygen signals obtained from X-ray energy dispersive spectroscopy (EDX), the failure was deemed to be caused by the incomplete removal of silicate photoresist polymer formed during the O2 plasma dry clean before copper plating. Based on this, we proposed to replace the dry clean with diluted HF clean prior to the copper plating, which can significantly remove the silicate polymers and increase the yield.

With semiconductor geometries approaching sub 10 nanometer gate levels in the not too distant future and with higher levels of integration, new ways of characterizing defects and examining the 3D distribution visually and elementally on the nanometer level are required to keep up with the demands of the modern FA lab. The purpose of this study is to demonstrate the workflow and show the results of an automated 3D STEM-EDX data acquisition & visualization system that can be utilized for the failure analysis of semiconductor devices.

Elementally characterizing intermetallic compounds (IMCs) to identify phases has routinely required relatively expensive transmission electron microscopy (TEM) analysis. A study was done characterizing IMCs using less expensive energydispersive x-ray (EDX) spectroscopy tools to investigate it as a practical alternative to TEM. The study found that EDX line scanning can differentiate phases by tracking changes in count rate as the electron beam of a scanning electron microscope (SEM) passes from one phase to another.

Cross sections of large Through Silicon Vias (TSV) and solder bumps are often prepared using the Focused Ion Beam (FIB). The high current Xe plasma ion source allows fast and precise target preparation of TSV with small diameter. Solder bumps can be accessed due to the high milling rate too. However, the high current milling by plasma FIB causes the worsening of the milled surface quality. An optimized FIB scanning strategy accompanied with the novel rocking stage for the sample tilting during the milling has been developed for the plasma FIB. Whole milling process is observed by the Scanning Electron Microscopy (SEM). Time to prepare a cross section is accelerated and the excellent quality is suitable for subsequent failure analysis. Also important is proper sample cleaving before FIB milling. Using an accurate method to cleave the sample prior to FIB preparation further reduces the overall sample preparation time. The high quality cross sections prepared using this new method are ready not only for SEM but also for EDX and EBSD analysis, either 2D or 3D, when combined with FIB slicing. Broadening the analysis to these techniques increases the obtainable information, allowing the arrangement of materials and their crystalline structure to be studied in a detail.

The analysis of thin layers in semiconductor components represents a central point in the quality control of semiconductor companies. Not only to control production processes, but to successfully operate also reverse engineering, reliable thin-film measurement methods are essential. In this work, non-destructive thin film EDX (energy dispersive X-ray micro analysis) software and μXRF (micro x-ray fluorescence analysis) were compared with TEM analysis. These methods ensure a high lateral resolution which is essential in the analysis of semiconductor structures. As an example, four different, for the semiconductor industry interesting, very thin coating systems in the nanometer range have been tested. In the individual cases best TEM detector contrast settings could be found, as well as optimum fluorescence lines settings on the EDX to minimize the errors. The TEM measurements, in thickness and composition, were compared to the thin film EDX software and the μXRF method results to determine their accuracy. It turns out that depending on the layer system recalibration with multilayer standards or at least with elemental standards is recommended. It could be shown that with μXRF and thin film EDX a reliable, rapid and non-destructive layer analysis is possible.

In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

In this work, energy-filtered TEM nano-beam diffraction (NBD) technique was used to evaluate channel strain profile in pMOS transistors suffering low Idsat issue. TEM and EDX analysis showed nickel deep diffusion into embedded SiGe source/drain. Such defect not only led to leakage current from S/D to substrate but might also reduce compressive strain induced to channel by eSiGe. Comparison of channel-direction strain between bad and good samples using NBD confirmed strain relaxation in bad sample which explained low Idsat as a result of reduced holes mobility.

In the context of the increasing complexity of materials used in semiconductor device processes, the STEM EDX technique is now used routinely. It can be used to discriminate stacked layers in advanced devices where STEM HAADF Z-contrast is not sufficient. Moreover, it allows a new use of planar preparation for layer investigation. The complexity of analyzed structures drives a need for 3D information which can also be obtained with the chemical information of the EDX analysis.

Solder bulging is detected on the exposed paddle of Device A after burn-in causing the affected units to fail the coplanarity criteria. The affected units show up at random burn-in board socket locations and occur with varying frequency. Potential causes are plotted through an Ishikawa diagram which reveal fusion and creep as the potential mechanisms behind the solder bulging phenomenon. This paper seeks to determine the mechanism behind the solder bulging phenomenon via a 2-step metallographic investigation through (i) material deformation characterization and (ii) deformation mechanism simulation. In material deformation characterization, visual inspection on affected units show that the solder bulge is generally circular and is located on the center of the exposed paddle. Moreover, SEM/EDX analysis reveal that the solder bulge is not caused by a foreign contaminant or a compositional anomaly in the solder plating. On the other hand, deformation mechanism simulation involves the metallographic comparison between controlled simulations of fusion and creep versus the actual unit with solder bulge. Metallographic inspection reveal that the grain size and grain shape of the solder bulge possess the characteristics of creep phenomenon. Additionally, investigation on the burn-in (BI) process conditions also supports creep over fusion as the mechanism behind the solder bulging phenomenon. The static stress induced by the socket on the package at elevated temperature caused the solder plating to creep towards the free area which is the hole on the bottom of the socket.

Although the overall spatial resolution of backscattered electron (BSE) imaging suffers in comparison to secondary electron (SE) imaging, its superior sensitivity to atomic number (Z) contrast and ability to image through overlying insulation levels can provide a complementary approach for imaging subtle buried defects. BSE enables the localization and imaging of embedded defects through overlying insulator levels without the risk of compromising them with reactive ion etch (RIE) or plasma etch exposure or by anisotropic wet chemical delayering process steps. Once the embedded defect is localized with BSE in situ, subsequent imaging by cross sectional Transmission Electron Microscopy (XTEM) combined with elemental analysis by energy dispersive X-Ray analysis (EDX) or electron energy loss spectroscopy (EELs) can be performed without the risk of introducing artifacts. In this work, BSE imaging was successfully employed to image embedded subtle defects in 32nm node technologies through overlying insulator films not possible with conventional SE imaging techniques.

Degradation of contact mating surfaces can produce a wide range of problems including intermittent failures and also full functional failures in all computer systems. This paper discusses the complexity involved with investigating the failure mechanism and root cause for intermittent memory failures on a product from end customers. Also discussed in detail is the approach of fault isolation followed by hypothesis development & physical analysis to arrive at root cause of failure. Fault isolation was achieved through register probing. Three major hypotheses were put forth namely plastic debris, misalignment and contact area issues. The physical analysis data collected through optical inspection, 2D x-ray, cross section and SEM analysis coupled with EDX to prove or disprove the hypotheses, revealed contact area corrosion in the form of nickel oxide. Contributors like gold plating thickness and plating porosity of the mating surfaces was verified to be not an issue in this case. Further analysis on the connector pins, memory modules and the contact area indicated damage to the connector pins leading to nickel exposure. The root cause for damage to the pins was analyzed to be a result of memory modules being inserted at an angle. Further studies are planned to look into design issues of connectors and memory modules to minimize damage to the contact area.

The corrosion phenomenon was found at the edge area of bond pad under OM images after dicing saw. Experiment showed that the corrosion was related with the feed speed of dicing saw. From SEM and OM results, there were some abnormal contaminations around the corrosive area. Auger and TEM with EDX system were used to characterize the corrosive region and the related Al pad corrosion mechanism was discussed. In this paper, Cu rich and O rich layers were identified by TEM and EDX, which could be induced by galvanic cell reaction.

This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

A failure analysis flow is developed for surface contamination, corrosion and underetch on microchip Al bondpads and it is applied in wafer fabrication. SEM, EDX, Auger, FTIR, XPS and TOF-SIMS are used to identify the root causes. The results from carbon related contamination, galvanic corrosion, fluorine-induced corrosion, passivation underetch and Auger bondpad monitoring will be presented. The failure analysis flow will definitely help us to select suitable methods and tools for failure analysis of Al bondpad-related issues, identify rapidly possible root causes of the failures and find the eliminating solutions at both wafer fabrication and assembly houses.