In today’s advanced technology world, electronic devices are playing a key role in modern semiconductor products to improve the energy proficiency. These devices are required to be contamination free especially on the bond pad with good adhesion before wire bonding process at the back end. Contamination on the bond pad leads to reliability issues such as pad corrosion, delamination and failure leading to leakage and open fails of electronic devices. Therefore, detection accuracy and sensibility of contamination is important. Auger analysis is the most suitable technique to check bond pad contamination. Auger electron spectroscopy has the capability of analyzing compositional information with excellent spatial resolution. However, charging, noise or artifact is known to be a major concern to the characterization of insulating materials. This paper outlines the strategy that has been utilized to minimize the artifact, noise or charging impact for Auger investigation on a smaller bond pad surrounded by imide passivation layers. The imide passivation layer normally causes the charging effect during Auger analysis, which makes the Auger analysis difficult to be proceed. In addition to that, the charging effect leads to inaccurate analysis. In this paper, we demonstrate a sample preparation method to minimize the charging and artifact of Auger analysis especially for small bond pads.

This paper discusses the basic physics of scanning acoustic microscopy, the counterfeit features it can detect, and how it compares with other screening methods. Unlike traditional optical inspection and IR and X-ray techniques, SAM can identify recycled and remarked chips by exposing ghost markings, fill material differences, delaminations from excessive handling, and popcorn fractures caused by trapped moisture. The paper presents several examples along with detailed images of these telltale signs of semiconductor counterfeiting. It also discusses the potential of developing an automated solution for detecting counterfeits on a large scale.

This paper presents a large-volume workflow for fast failure analysis of microelectronic devices. The workflow incorporates a stand-alone ps-laser ablation tool and a FIB-SEM system. As implemented, the picosecond laser is used to quickly remove large volumes of bulk material while the Xe plasma FIB provides precise end-pointing to the feature of interest and fine surface polishing after laser ablation. The paper presents several application examples, including a full workflow to prepare artefact-free, delamination-free cross-sections in an AMOLED mobile display and the preparation of devices and packages (including flip chips) of varying size. It also covers related issues such as CAD navigation, data correlation, and the use of bitmap overlays for end-pointing.

Vertical-cavity surface-emitting lasers (VCSELs) have many advantages over edge-emitting devices, but they tend to be more sensitive to increasing current density both in lifetime and reliability. To better understand this relationship, the authors investigated the cause of 35 failures involving GaAs-based oxide-confined VCSELs. This paper presents a summary of the procedures, methods, and equipment used, the defects and damages observed, and the root causes behind each failure. The authors followed a standard failure analysis workflow consisting of PEM and OBIRCH fault isolation, plan view TEM to confirm the location and distribution of defects, and cross-sectional TEM (XTEM) to determine the profile of a defect at a specific site. All failures examined could be attributed to one of four basic failure mechanisms: burnout due to ESD, dislocations, oxide diffusion, and oxide delamination.

Currently gaps in non-destructive 2D and 3D imaging in PFA for advanced packages and MEMS exist due to lack of resolution to resolve sub-micron defects and the lack of contrast to image defects within the low Z materials. These low Z defects in advanced packages include sidewall delamination between Si die and underfill, bulk cracks in the underfill, in organic substrates, Redistribution Layer, RDL; Si die cracks; voids within the underfill and in the epoxy. Similarly, failure modes in MEMS are often within low Z materials, such as Si and polymers. Many of these are a result of mechanical shock resulting in cracks in structures, packaging fractures, die adhesion issues or particles movements into critical locations. Most of these categories of defects cannot be detected non-destructively by existing techniques such as C-SAM or microCT (micro x-ray computed tomography) and XRM (X-ray microscope). We describe a novel lab-based X-ray Phase contrast and Dark-field/Scattering Contrast system with the potential to resolve these types of defects. This novel X-ray microscopy has spatial resolution of 0.5 um in absorption contrast and with the added capability of Talbot interferometry to resolve failure issues which are related to defects within organic and low Z components.

Failure Analysis labs involved in customer returns always face a greater challenge, demand from customer for a faster turnaround time to identify the root cause of the failure. Unfortunately, root cause identification in failure analysis is often performed incompletely or rushing into destructive techniques, leading to poor understanding of the failure mechanism and root-cause, customer dissatisfaction. Scanning Acoustic Tomography (SAT), also called Scanning Acoustic Microscope (SAM) has been adopted by several Failure Analysis labs because it provides reliable non-destructive imaging of package cracks and delamination. The SAM is a vital tool in the effort to analyze molded packages. This paper provides a review of non-destructive testing method used to evaluate Integrated Circuit (IC) package. The case studies discussed in this paper identifies different types of defects and the capabilities of B-Scan (cross-sectional tomography) method employed for defect detection beyond delamination.

This paper discusses the implementation of GHz-Scanning Acoustic Microscopy (GHz-SAM) into a wafer level scanning tool and its application for the detection of delamination at the interface of hybrid bonded wafers. It is demonstrated that the in-plane resolution of the GHz-SAM technique can be enhanced by thinning the sample. In the current study this thinning step has been performed by the ion beam of a ToF-SIMS tool containing an in-situ AFM, which allows not only chemical analysis of the interface but also a well-controlled local thinning (size, depth and roughness).

This paper describes the detailed sample preparation of a solder joint at the level between a semiconductor package and board. Different sample preparation techniques are described and compared. Preparing and targeting a large sample area containing multiple solder bumps is discussed. The sample preparation methods will then be confirmed by advanced structural characterization and strain measurement. The presence of strain is associated with the development of cracks and delamination at the solder joint interface.

FIB/SEM and TEM are standard characterization techniques for evaluation of process modification of microelectronics samples. In this paper, artefacts from these techniques are studied. The sample preparation methods are optimized to avoid damages. Seal-ring structures are chosen as an example in this study to show artefacts and difficulties in SEM and TEM observations. Two cases of artefacts are considered: one with TEM sample preparation followed by TEM imaging, and the other one with SEM observations after FIB cross-sectioning. In the first case, electronic chips that failed during stress tests are investigated, while in the second case a part has been dismissed during robustness qualification test. In the former, thickness of TEM lamellae has been evidenced as a key factor for delamination between layers under beam, whereas in the latter, it was observed that the electron beam lead to a shrink of oxide layers, which induced the break of underlying contacts.

In this paper, an automated contactless defect analysis technique using Computer Vision (CV) algorithms is presented. The proposed method includes closed-loop control of optical tools for automated image collection, as well as advanced image analysis methods to improve image quality and detect potential defects. As an example, the technique was successfully used to identify delamination defects along the perimeter of a large test chip.

GHz scanning acoustic microscopy (GHz-SAM) was successfully applied for non-destructive evaluation of the integrity of back end of line (BEOL) stacks located underneath wire-bond pads. The current study investigated two sample types of different IC processes. Realistic bonding defects were artificially induced into samples and the sensitivity of the acoustic GHz-microscope towards defects in BEOL systems was studied. Due to the low penetration depth in the acoustic GHz regime, a specific sample preparation was conducted in order to provide access to the region of interest. However, the preparation stopped several microns above the interfaces of interest, thus avoiding preparation artifacts in the critical region. Cratering related cracks in the bond pads have been imaged clearly by GHz-SAM. The morphology of the visualized defects corresponded well with the results obtained by a chemical cratering test. Moreover, delamination defects at the interface between ball and pad metallization were detected and successfully identified. The current paper demonstrates non-destructive inspection for bond-pad cratering and ball-bond delamination using highly focused acoustic waves in the GHz-band and thus illustrates the analysis of micron-sized defects in BEOL layer structures that are related to wire bonding or test needle imprints.

NCF (Non Conductivity Film) is a material used for under-fill purpose in the TSV (Through Silicon Via) process, and is a key material for ensuring TSV 3D Package (PKG) reliability. Among the types of defects generated by the NCF, the most typical type is delamination. Particularly in NCF delamination frequently occurs during reliability test, we analyzed chemical state change of NCF according to reliability test step/condition by utilizing FTIR and TMA. Through these studies, we clarify the cause of Delamination.

Through Silicon Via (TSV) is the most promising technology for vertical interconnection in novel three-dimensional chip architectures. Reliability and quality assessment necessary for process development and manufacturing require appropriate non-destructive testing techniques to detect cracks and delamination defects with sufficient penetration and imaging capabilities. The current paper presents the application of two acoustically based methods operating in the GHz-frequency band for the assessment of the integrity of TSV structures.

This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

This paper describes the detection capability of micro delamination in ICs according to the transducer frequency of SAM (Scanning Acoustic Microscopy) equipment through a case study of non-destructive failure analysis. The analysis of scanning acoustic microscopy is non-destructive, but is difficult to define micro de-lamination or micro crack. In this study, two SAM systems and various transducer frequencies were used to detect micro de-lamination on the lead finger area. In the results of non-destructive analysis by utilizing two systems, one SAM detected the micro delamination but the other SAM did not define micro delamination with C-scan mode. To confirm an accurate delamination phenomenon, we analyze the destructive analysis under cross-sectional inspection and the micro de-lamination was observed. The cause of non-detection for micro delamination is not due to the difference between equipments, but due to the transducer frequency. This paper will be concluded with a discussion on what kind of transducer frequency are selected according to distance from package surface to chip surface, package materials, and micro de-lamination thickness.

FA cannot consist of simply jumping to conclusions. The FA process is validated through correlation with the initial failure and through interpretation of the obtained results, subjective by definition. This paper illustrates the difficulty of analyzing complex failures caused by multiple factors, including wafer fabrication, assembly, and application conditions. Inter-Layer Dielectric (ILD) delamination was experienced on various ICs from the same 250nm technology. A complete set of techniques (C-SAM, laser and optical microscopy, SEM, FIB cross-sections, TEM, EFTEM, SIMS, Auger, delineation) was used as different pieces of the same puzzle to reveal the multiple factors contributing to the ILD delamination failures. Due to the subtle nature of some of the underlying causes, defining an accurate FA approach with appropriate sample preparation and accurate device traceability was critical to understanding this complex, multivariate issue.

This study investigated the origin of detrimental high ohmic behavior of contacts by means of analytical electron microscopy. The root cause for the high resistivity could be identified as delamination of the contact bottom in the nanometer range. Based on the results, we were able to establish a method to identify thin oxide layers using analytical methods without being able to spatially resolve them in a combined focused ion beam instrument and scanning electron microscope.

A new approach to reliability improvement and failure analysis on ICs is introduced, involving a specifically developed tool for Topography and Deformation Measurement (TDM) under thermal stress conditions. Applications are presented including delamination risk or bad solderability assessment on BGAs during JEDEC type reflow cycles.

Negative resistance drift in thick film chip resistors in high temperature and high humidity application conditions was investigated. This paper reports on the investigation of possible causes including formation of current leakage paths on the printed circuit board, delamination between the resistor protective coating and laser trim, and the possibility of silver migration or copper dendrite formation. Analysis was performed on a set of circuit boards exhibiting failures due to this phenomenon. Electrical tests after mechanical and chemical modifications showed that the drift was most likely caused by moisture ingress that created a conductive path across the laser trim.

Failures in printed circuit boards account for a significant percentage of field returns in electronic products and systems. Conductive filament formation is an electrochemical process that requires the transport of a metal through or across a nonmetallic medium under the influence of an applied electric field. With the advent of lead-free initiatives, boards are being exposed to higher temperatures during lead-free solder processing. This can weaken the glass-fiber bonding, thus enhancing conductive filament formation. The effect of the inclusion of halogen-free flame retardants on conductive filament formation in printed circuit boards is also not completely understood. Previous studies, along with analysis and examinations conducted on printed circuit boards with failure sites that were due to conductive filament formation, have shown that the conductive path is typically formed along the delaminated fiber glass and epoxy resin interfaces. This paper is a result of a year-long study on the effects of reflow temperatures, halogen-free flame retardants, glass reinforcement weave style, and conductor spacing on times to failure due to conductive filament formation.