3D package technologies like Multi-Chip Modules (MCM) and System in Package (SIP) have been in the semiconductor package industry for some time now. At the advent these technologies were mostly incorporated for digital solutions, however more recently these packaged solutions have been increasingly used for analog technologies specifically for power applications. With these packaged innovations increasingly adapted, Failure Analysis (FA) takes a central stage not just in supporting customer returned devices but also in root cause investigations leading to new product development, qualifications and ramp to market. These 3D heterogeneous packages however pose multiple newer challenges to FA compared to traditional single chip package solutions. This paper presents some of these Failure Analysis challenges encountered most commonly on analog 3D power modules and talks about possible solutions to overcome them with case studies. Further it also addresses solution that will require FA to think and adapt improved tool sets whether it’s newer solutions that market has to offer or modification to existing approach including chemical recipes, decapsulation methods, etc. to navigate these intricate packages.

Nowadays, semiconductor components are widely used in home electronic appliances, vehicles, industrial motor controls and beyond. The performance and reliability of these components are becoming more crucial and critical. Generally, a semiconductor component consists of lead frames, wires, dies and die attaches. Within the die, the die backside metallization, also known as “BSM,” plays an important role in electronic component manufacturing. The BSM is a layer that promotes good adhesion, electrical properties and long-term stability as a conductive pathway to the circuits. As such, the inspection on BSM is needed to ensure robustness. Several conventional methods have been developed to analyze the die backside metallization. In this paper, we will discuss the inspection on backside metallization and comparison among five sample preparation methods: mechanical cross section with ion milling, mechanical cross section with FIB cleaning, die frontside decapsulation with FIB cut from die surface and FIB cut from die sidewall, and component frontside lapping with FIB from the remaining silicon. Result comparison will be discussed in case studies and the advantages and disadvantages of the five methods will be compared.

Failure to apply the proper systematic analysis procedure can result in loss of valuable evidence required to understand the root cause of package failures. For example, in the case of marginal current leakage fail, decapsulation from package front-side may result in loss of the electrical failure signal so that root cause of the leakage failure cannot be understood. In such case, a systematic backside fault isolation method can improve the success rate of isolating the defect. These electrical failures are often due to zero solder bond line thickness (BLT), or filler particle compression on the die, which are key assembly defects encountered in clip style surface mount packages (SMX). In this paper, the first case study is to determine the failure mechanism of an electrical short. A silicon micro-crack propagating through the junction at the dimple clip center, which is due to the ultra-thin solder BLT close to zero micron is found to be the root cause of failure. The second case presents the failure mechanism for a low leakage fail. The pointed tip of a silica filler particle compressed on the die surface leads to excessive leakage.

As the electronics industry moves towards miniaturization, the semiconductor industry provided packaging innovations to meet the demands for smaller footprints. One of the packaging solutions is the small outline transistor (SOT) which is widely used in various applications including automotive engine downsizing. Decapsulation of small packaged devices like a 1.3mm by 2.9mm SOT is one of the greatest challenges in failure analysis. The destructive nature of decapsulation may cause inadvertent and permanent damage, hindering further electrical verification on the unit. In this paper, a novel method for decapsulating SOT devices is presented utilizing the use of acrylic molding to avoid damage on the units during decapsulation process. Results show that the use of acrylic molding is an effective method in decapsulating SOT packaged devices maintaining die functionality, hence, addressing the decapsulation issues and risks caused by other existing decapsulation methods.

Decapsulation of silver wire bonded packages with known techniques often results in damaged silver wires. The chemical properties of silver and silver compounds make silver bond wire inherently susceptible to etching damage by acid, conventional plasma, and oxygen-based Microwave Induced Plasma (MIP). In this paper we solve this problem by developing a specific decapsulation chemistry, based on a hydrogen-containing MIP, for artifact-free decapsulation of silver wire bonded packages.

An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.

An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.

In the back-end assembly process, all of the packages will be tested prior to disposition to the customers in order to filter out any device with failure. For a reject unit with an unknown failure mechanism, it will be subjected to a comprehensive failure analysis (FA) to identify the root cause of the failure. Non-destructive verification, following by front-side decapsulation and internal physical inspection is the common way to visualise and identify the physical defect that usually causes the failure of a device during the back-end assembly process. For certain failures, visualization of the defect might not be straight forward after the decapsulation because the defect may be embedded or buried underneath a layer or wedge bond on the die. In this case, a more complicated FA analysis flow which comprises various precision techniques such as parallel lapping, hotspot localisation and focused-ion-beam (FIB) analyses will be needed to thin down the top layer/wedge bond for a precise localisation of the defect prior to precision analysis by FIB. However, the process to thin down the top layer/wedge bond with an exposed die of a partially decapsulated package is a tricky job as artefacts such as crack/scratches on die are likely to be introduced during the process of polishing. Also it is relatively difficult to control the thickness and levelling of the top layer/wedge bond during the thinning process. In this work, we developed a method that allows the analyst to re-cap the partially decapped package, and also to precisely measure and thin down the top layer to an accuracy of less than < 2um without the introduction of artefacts.

Gallium Arsenide (GaAs) integrated circuits have become popular these days with superior speed/power products that permit the development of systems that otherwise would have made it impossible or impractical to construct using silicon semiconductors. However, failure analysis remains to be very challenging as GaAs material is easily dissolved when it is reacted with fuming nitric acid used during standard decapsulation process. By utilizing enhanced chemical decapsulation technique with mixture of fuming nitric acid and concentrated sulfuric acid at a low temperature backed with statistical analysis, successful plastic package decapsulation happens to be reproducible mainly for die level failure analysis purposes. The paper aims to develop a chemical decapsulation process with optimum parameters needed to successfully decapsulate plastic molded GaAs integrated circuits for die level failure analysis.

Accurate root cause determination of integrated circuit devices necessitates the preservation of evidence during failure analysis. Identifying the cause of systemic defects requires capturing physical evidence provided by very few customer returns. Each piece of physical evidence is valuable due to the scarcity of returns in most cases less than 1 ppm. Harvesting infrequent physical evidence requires that each attempt to decapsulate a fail unit has a high probability of retaining the material that caused the defect. A measured method that retains the critical evidence is the fastest way to solve a defect driven systemic failure mechanism because one gathers the evidence more efficiently. This paper presents two case studies of improved evidence gathering using halogen-free microwave induced plasma (MIP) decapsulation during the root cause investigations. This relatively new method of decapsulation enabled us to preserve evidence, including any changes to the metal and die surface structures along with the presence of contaminants or by-products of failure mechanisms.

When it comes to complex system-in-package (SiP) with a wide spectrum of materials and packaging structures integrated into a single module, decapsulation and the following failure analysis become extremely complex. Previous work published by the authors' group has demonstrated that a halogen-free microwave induced plasma (MIP) system has great advantage compared to the conventional techniques mentioned before. This paper explores the applicability of the halogen-free MIP on the most complex SiP module decapsulation. Applications in special structures in SiP include 3D stacked-die, gallium arsenide, surface acoustic wave (SAW) and bulk acoustic wave filters, and copper re-distribution layer. The halogen-free MIP decapsulation process can expose and preserve all the dies and passive components as well as the original failure sites, which proves to be key to ensuring a high success rate in SiP failure analysis.

Failure analysis of automotive semiconductor devices requires highly reliable techniques to guaranty the success of artifact-free decapsulation with high repeatability and reproducibility. With the introduction of new qualification standards, new mold compounds, and new packaging structures, advanced decapsulation tools are needed to enable failure analysis to achieve a high success rate. Microwave Induced Plasma (MIP) machine has been developed as an advanced decapsulation solution. The CF4-free MIP etching ensures artifact-free exposure of bond wires made of new materials, the die, passivation, bond pads, and original failure sites. The high mold compound etching rate, high etching selectivity of mold compound to wire/pad/passivation/die, and the fully automatic process are the unique features of MIP decapsulation. Comparisons are made between acid, conventional plasma with CF4, and CF4-free MIP decapsulation. Multiple case studies are discussed that address challenging automotive semiconductor device decapsulation, including bare copper wire, copper redistribution layer, exposed power copper metal, stitch bond on silver plated leadframe, complex mold compound, Bond-Over-Active-Circuit, eWLB, and localized decapsulation.

We present experimental results of IC package decapsulation carried out using Ar and O2 gas mixture remote plasma generated by atmospheric microwave plasma needle (“a-MPN”). Depth etch rate of up to 6.5 µm/min and volume etch rate of up to 0.1 mm3/min were shown to be obtained by a-MPN process operated at 15 W microwave power. SEM imaging suggested no damage to the bonding wire, pads, or passivation.

The focus of this paper is to present an interesting case study involving Vishay wire-wound (WSC model) resistor failures, which affected a significant number of production and fielded assemblies. The failures were considered “mission critical”, which was the primary driver necessitating root cause analysis. A disciplined approach to the failure analysis effort was established, which resulted in root cause determination and the generation of appropriate corrective actions. This paper will highlight a non-conventional decapsulation method used to preserve the integrity of the fragile resistive element and a “lucky break” that was instrumental in linking the supplier’s actions to the failures.

The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Decap methods which have been used for copper wire packages are not effective for silver wire packages, and the authors recognized the need for the development of a novel method. This paper discusses the development of various processes to decap silver wire packages with acid. The first decap method developed for a silver wire package was to add hydrochloric acid to fuming nitric acid. This method proved insufficient to prevent silver wire from dissolving when solution temperature is 60 degree. The authors then developed the Saturation Etch method for decapsulating silver wire packages using a chemical solution. When dissolution amount of silver wire put in normal fuming HNO3 is defined as 100%, the authors were able to achieve its reduction to less than 3% by using saturated acid. This method is also effective for copper wire packages, and damages to wires can be minimized by dissolving copper into acid.

LASER techniques are widely used for pre-opening in combination with a final manual or automated wet chemistry decapsulation. Even if most of the ICs may be opened today, and if opening the recently introduced Ag wires packages have been solved with novel chemical recipes, the need for a greener and safer solution is still there. Plasma techniques combined with LASER can be a promising solution to these challenges. In this paper, after a presentation of the state of the art of the different techniques available in laboratories nowadays, the latest solution combining LASER and acid or plasma etching is presented. The paper compares the results obtained with these solutions on Cu an Ag wires devices with pros and cons for each solution. The results presented show the benefits, the constraints and the limitations of each technique regarding the different types of wires used in industry.

With the introduction of new packaging technologies and the great variety of semiconductor devices, new decapsulation tools are needed to improve failure analysis with a higher success rate, and to improve quality control with a higher confidence level. Conventional downstream microwave plasma etchers use CF4 or other fluorine containing compounds in the plasma gas that causes unwanted overetching damage to Si3N4 passivation and the Si die, thus limiting its use in IC package decapsulation. The approach of atmospheric pressure O2-only Microwave Induced Plasma (MIP) successfully solves the fluorine overetching problem. Comparison between MIP, conventional plasma, acid etching based on several challenging decapsulation applications has shown the great advantage of MIP in preserving the original status of the die, wire bonds, and failure sites. One of the challenging failure analysis cases is Bond-Over-Active-Circuit (BOAC) devices with exposed thin copper metallization traces on top of Si3N4 passivation. The BOAC critical die structures present a challenge to both conventional plasma and acid decapsulation. The use of MIP to solve the BOAC device decapsulation problem will be discussed in detail through multiple case studies. It appears that the MIP machine is the only approach to decapsulate BOAC devices without causing any damage to the exposed copper on passivation critical structure, which demonstrates the failure analysis capabilities of the MIP system.

Over the past several years there has been a large industry wide effort to change over from gold bonding wires to copper in order to minimize production costs. In certain cases this is not possible due to the relatively high hardness values of Cu [1], which leads to reliability issues in the manufacturing process. Silver (Ag) wire has been proposed and successfully implemented in many instances where Cu wire was not practicable. Unfortunately, currently integrated decapsulation methods severely damaged or destroyed the silver wires and bonds, making it impossible to perform production controls and failure analysis. In this article we present a reliable and repeatable automated method to expose these die and wire bonds. By adding a dilute iodine solution to the nitric acid in an acid decapsulator, these packages can be fully opened without degrading the silver wires, allowing both mechanical and electrical testing on these devices.