This paper reports the novel application of Plasma Focused Ion Beam (pFIB) to reveal subtle defects in advanced technology nodes. Two case studies presented, both of which alter the standard work procedure in order to find the defects. The first case highlights the precise milling capability of pFIB in discovering the metal buried via void that is easy-to-miss by standard failure analysis (FA) practice. The second utilizes pFIB circuit edit process to facilitate electrical isolation in pinpointing the exact failure location and thus enables identifying the defect more efficiently.

Reproducible laser-assisted metal deposition with copper hexafluoroacetylacetonate trimethylvinylsilane Cu(hfac) (TMVS) has been demonstrated on a range of relevant semiconductor insulating material surfaces including silicon dioxide (SiO 2 ), crystalline silicon (c-Si), and organic package material such as polyimide and printed circuit board (PCB) FR- 4. A key to reliable and chemically efficient growth is a novel copper chemistry delivery methodology using direct precursor pulsing. The laser power conditions for deposition are strongly correlated to the substrate material, with increased power for the more thermally conductive samples (0.8 – 1.0 W) and significantly less for packaging materials (50 mW). The laser-assisted copper growth results and material properties are comparable to the published literature. Examples of circuit modifications using this methodology demonstrate its valuable role in the future of circuit edit.

The workflow of backside IC circuit edits using low and high ion-beam energy is investigated. The imaging capabilities using a high keV beam are superior to that of lower beam energy, even when using low beam currents, on typical ion beam microscopes. In this work, we will test the parametric shift of IC components following the use of 5 keV Gallium Focused Ion Beam (FIB) to expose Shallow Trench Isolation (STI), depositing a protective dielectric layer, and then switching to 30 keV FIB to perform device alteration. Electrical testing results show that the devices exhibit only a minor parametric shift. We present a case study, performing circuit edit on a 7 nm process node using the proposed workflow. Finally, we discuss the advantages of the proposed workflow.

The characterization of back side illumination (BSI) image sensors is challenging because of the unique construction of such sensors with silicon on top. A novel method for BSI image sensor characterization is presented in this paper. The proposed approach is based on backside circuit editing using ion beam and optical imaging techniques. This provides access to buried conductors and creates probe points for measurements that can be made using an optical, electron beam, or mechanical micro/nano prober.

Passive voltage contrast (PVC) is widely used to detect underlying connectivity issues between metals based on the brightness of upper metals using scanning electron microscopy (SEM) or focused ion beam (FIB). [1] However, it cannot be applied in all cases due to the uniqueness of each case where brightness alone is insufficient to tell leakage location. In this study, propose a simple technique using platinum (Pt) marking as a circuit edit (CE) technique to alter metal PVC to identify the actual leakage location. Conventional SEM and PVC contrast imaging are unable to pinpoint exact defects without data confirming the leakage from nano-probing such as Atomic Force Probing (AFP) or SEM base nano-probing (NP) [2]. Using this method, we can improve the analysis cycle time by direct analysts the defective location in SEM, while also saving tool cost.

Focused Ion Beam (FIB) chip circuit editing is a well-established highly specialized laboratory technique for making direct changes to the functionality of integrated circuits. A precisely tuned and placed ion beam in conjunction with process gases selectively uncovers internal circuitry, create functional changes in devices or the copper wiring pattern, and reseals the chip surface. When executed within reasonable limits, the revised circuit logic functions essentially the same as if the changes were instead made to the photomasks used to fabricate the chip. The results of the intended revision, however, can be obtained weeks or months earlier than by a full fabrication run. Evaluating proposed changes through FIB modification rather than proceeding immediately to mask changes has become an integral part of the process for bringing advanced designs to market at many companies. The end product of the FIB process is the very essence of handcrafted prototyping. The efficacy of the FIB technique faces new challenges with every generation of fabrication process node advancement. Ever shrinking geometries and new material sets have always been a given as transistor size decreases and overall packing density increases. The biggest fundamental change in recent years was the introduction of the FinFET as a replacement for the venerable planar transistor. Point to point wiring change methodology has generally followed process scaling, but transistor deletions or modifications with the change to Fins require a somewhat different approach and much more careful control due to the drastic change in height and shape. We also had to take into consideration the importance of the 4 th terminal, the body-tie, that is often lost in backside editing. Some designs and FET technology can function acceptably well when individual devices are no longer connected to the bulk substrate or well, while others can suffer from profound shifts in performance. All this presents a challenge given that the primary beam technology improvements of the fully configured chip edit FIB has only evolved incrementally during the same time period. The gallium column system appears to be reaching its maximum potential. Further, as gallium is a p-type metal dopant, there are limitations to its use in close proximity to certain active semiconductor devices. Amorphous material formation and other damage mechanisms that extend beyond what can be seen visually when endpointing must also be taken into account [1]. Device switching performance and even transmission line characteristics of nearby wiring levels can be impacted by material structural changes from implantation cascades. Last year our lab participated in a design validation exercise in which we were asked to modify the drive of a multi-finger FinFET device structure to reduce its switching speed impact on a circuit. The original sized device pulled the next node in the chain too fast, resulting in a timing upset. Deleting whole structures and bridging over/around them is commonly done, but modifications to the physical size of an FET device is a rare request and generally not attempted. It requires a level of precision in beam control and post-edit treatment that can be difficult to execute cleanly. Once again during a complex edit task we considered the use of an alternate ion beam species such as neon, or reducing the beam energy (low kV) on the gallium tool. Unfortunately, we don’t yet have easy access to a versatile viable replacement column technology grafted to a fully configured edit station. And while there should be significantly reduced implant damage and transistor functional change when a gallium column FIB is operated at lower accelerating potential [2], the further loss of visual acuity due to the reduced secondary emission, especially when combined with ultra-low beam currents, made fast and accurate navigation near impossible. We instead chose the somewhat unconventional approach of using an ultra-low voltage electron beam to do much of the navigation and surface marking prior to making the final edits with the gallium ion beam in a dual-beam FIB tool. Once we had resolved how to accurately navigate to the transistors in question and expose half of the structure without disturbing the body-tie, we were able to execute the required cut to trim away 50% of the structure and reduce the effective drive. Several of the FIB modified units functioned per the design parameters of a smaller sized device, giving confidence to proceed with the revised mask set. To our surprise, the gallium beam performed commendably well in this most difficult task. While we still believe that an inert beam of similar characteristics would be preferable, this work indicates that gallium columns are still viable at the 14 nm FinFET node for even the most rigorous of editing requirements. It also showed that careful application of e-beam imaging on the exposed underside of FinFET devices could be performed without degrading or destroying them.

The characterization of Back Side Illumination (BSI) Image Sensor is challenging because of its unique construct with silicon on top. A novel approach for the BSI Image sensor characterization will be presented in this paper. The proposed approach utilizes the circuit editing through the silicon (backside) by ion beam and optical imaging. This technique allows access to the buried conductors and creates probe points for measurements, which are typically performed by an optical prober, electron beam prober or a mechanical micro/nano prober.

Focused Ion Beam (FIB) circuit edit allows for rapid prototyping of potential semiconductor design changes without the need to run a full manufacturing cycle in a semiconductor Fab. By FIB editing a completed module, thorough testing on the bench or in a full system can be achieved. Logic can be toggled, validation of speed enhancements performed, and constructive and destructive failure analysis can be enabled. In order to fulfill all the needs of clients in a rapidly evolving SOC driven market, simply modifying existing devices by “rewiring” circuits is becoming insufficient. Often the team is tasked with making very repeatable structures to aid the circuit analysis group. These include relatively precise resistors for tuning RF circuits (part of an RC network), adding known loads or delays, et cetera. Naturally resistive FIB deposited metal lines connected to the existing circuitry can be used in this capacity. FIB chip edit is considered to be a “Direct Write” process. The beam pattern in conjunction with process gases defines the regions of milling and deposition. Unfortunately, FIB edit is rarely an exact science. In many cases, a number of characteristics seem to be outside the realm of precise repeatable control. This is evident not only in individual tool operational logs but also in FIB tool matching, where maintaining identical system performance within the lab is difficult or nearly impossible. These characteristics are highly dependent on precursor reservoir composition and flow, surface adsorption conditions, beam patterning integrity, and the total interaction space of competing back sputtering during the new material structure formation. Due to these factors, the shape, composition and electrical performance of metal and insulator depositions vary over an often unacceptable range. As a result, we were not meeting the needs of some critical customer applications. Direct written precision resistive structures displayed several issues for which iterative edits were required to compensate for variability. When attempting to create an exact resistance, this process was not reliable, nor was it repeatable enough for accurate circuit performance trimming. Space-constrained serpentine resistors or multiple discrete resistors side-by-side showed the greatest process variability. Metal deposition processes tend to be somewhat self-limiting, so thick boxprofile lines are difficult to form. Conductive material deposited outside of the pattern definition (overspray) results in line-to-line leakages. Attempts to remove the overspray thru ion beam assisted etch-back tends to damage the deposited conductors and underlying insulators. The low-k region between lines can become cross-linked, experience gallium doping, and become tungsten impregnated. This lowered the resistivity of the insulator, increased the resistivity of the conductor, and produced variability in the device which was especially an issue when dealing with varying initial substrates. GLOBALFOUNDRIES began a project to create a more robust repeatable resistive structure by removing several variables. Rather than direct writing lines onto a top surface layer, a confined deposition based on the concepts of dual damascene processing used with copper layers in modern semiconductor fabrication will be employed. The damascene process begins with the definition of a box to be filled with a conductive material. The process of ion beam gas assisted anisotropic etching/milling has a far more predictable outcome than ion beam induced deposition. It is possible to create a surface box mill or even a deep drilled via of desired dimensions with a more consistent repeatability. Deposition of tungsten into a confined region using, for example, a W(CO)6 precursor and a Ga+ ion beam results in an excellent via fill. Using this behavior, precision resistors can be created with metal deposition within the trenches which are created by the gas assisted mill. An enclosed space can be filled nearly void-free, and has repeatable electrical parameters. The self-limiting factors with tungsten deposition go away as sputtered material becomes trapped within the well resulting in a near limitless Zheight potential. The constant dielectric with a uniform and contained tungsten fill can allow for a well-defined resistivity for the FIB deposited tungsten material. Having a known resistivity, calculation of dimensions for resistive and inductive structures during the design process becomes feasible. With process variability under control, structures can be formed reliably enough to offer this as a service to customers.

Backside silicon removal provides an avenue for a number of modern non-destructive and circuit edit techniques. Visible light microscopy, electron beam microscopy, and focused ion beam circuit edit benefit from a removal of back side silicon from the integrated circuit being examined. Backside milling provides a potential path for rapid sample preparation when thinned or ultrathinned samples are required. However, backside milling is an inherently destructive process and can damage the device function, rendering it no longer useful for further nondestructive analysis. Recent methods of backside milling do not guarantee device functionality at a detected end point without a priori knowledge. This work presents a methodology for functional end point detection during backside milling of integrated circuit packaging. This is achieved by monitoring second order effects in response to applied device strain, which guide the milling procedure, avoiding destructive force as the backside material is removed. Experimental data suggest a correlation between device power consumption waveforms and second order effects which inform an in situ functional end point. Keywords: functional end point, side-channel analysis, backside thinning, milling, machine learning, second order effects

Secondary electron detector (SED) plays a vital role in a focused ion beam (FIB) system. A successful circuit edit requires a good effective detector. Novel approach is presented in this paper to improve the performance of such a detector, making circuit altering for the most advanced integrated circuit (IC) possible.

In the semiconductor chip manufacturing industry, a method of evaluating characteristics by applying a direct circuit edit at an already manufactured chip level is widely used in order to shorten the product development time and release the product to the market in a short time. [1] This is because, when the fab process is performed by modifying the mask to improve the characteristics as in the conventional method, it takes a lot of time and cost for feedback. Feedback of semiconductor characteristics through circuit edit can save 10-20 times in terms of cost and time. As the process becomes more complex and the pattern size becomes smaller, its benefits become even greater. However, when the chip level circuit edit is applied to the Chip Scale Package (CSP) IC, it is very difficult to apply a general method of the frontside circuit edit, so that the success rate of the circuit edit is lowered. In order to solve this problem, a circuit edit method in the backside direction of the chip has been attempted for many years. [2, 3] However, the backside circuit edit (BCE) has more difficulties than the frontside circuit edit. A typical issue is how to uniformly and precisely control and remove the backside Si of the circuit edit area. The following three points should be considered for this. First, the uniformity of the remaining silicon thickness should be high. Second, it is necessary to control the thickness of remaining silicon to an appropriate thickness in the process of removing backside silicon. Third, it is important not to damage the peripheral circuit during etching and deposition. In this paper, we propose a method to increase the backside circuit edit success rate of CSP IC using Al or Cu metal by controlling these three factors effectively.

This paper describes a circuit editing procedure in which the authors used a gallium column Focused Ion Beam (FIB) tool to divide a merged 32nm multi-finger planar transistor into two separate operating components. Rather than rely on live imaging or the various endpoint detection techniques commonly used during an active mill, the authors opted for a ‘blind’ dose-driven technique. The paper explains how the authors made multiple attempts on practice material in order to determine the exact beam placement location and the depth of cut required to perform the operation with a minimum of lateral damage. The loss of a pair of poly gate fingers in the middle of the multi-gate structure seemed to have minimal impact on the final electrical parameters and the separate data paths worked per design specifications.

Backside circuit edit (CE) remains a crucial failure analysis (FA) capability, enabling design modifications on advanced integrated circuits. [1-9] A key requirement of this activity is to approach the active transistor layer of the silicon through the removal of the silicon substrate without exposing or damaging critical transistor features. Several methods have been previously developed to enable or assist with the process with either global or locally targeted techniques for thinning the silicon substrate. These methods employ mechanical methods, laser based techniques (continuous or pulsed), or chemical assisted focused ion beam (FIB) etching to accomplish the thinning. Each of these methods presents different strengths and weaknesses, from their reliability to complexity, but very few techniques provide a precise and accurate quantitative measure of the remaining silicon thickness (RST). Here, we will discuss the use of a FIB with XeF2 for backside Si removal, and the development of an in-situ, accurate measurement of RST.

Widespread adoption and significant developments in Focused Ion Beam technology has made FIB/SEM instrumentation a commonplace sample preparation tool. Fundamental limitations inherent to Ga ion species complicate usage of Ga+ FIB instruments for the modification of semiconductor devices on advanced technology nodes. Said limitations are fueling interest in exploring alternative primary species and ion beam technologies for circuit edit applications. Exploratory tests of etching typical semiconductor materials with Xe ion beams generated from two plasma ion sources confirmed advantages of Xe+ as a potential ion species for gas-assisted etching of semiconductor materials, but also revealed potential complications including, swelling of metal and Xe+ retention within the material arising from excessive Xe ion beam current density.

As the Internet of Things, smart factories and autonomous driving increase the demand for low-price radar sensors, the authors address this need by developing a 24 GHz short range radar in standard bulk silicon CMOS technology for mass market production. CMOS technology enables cost reduction and efficient system integration compared to former GaAs and current SiGe solutions. Design for failure analysis (DFFA) is implemented in the low-noise amplifier (LNA) of the radar to identify and compensate process deviations. It consists of scalable capacitor structures and is executed using focused ion beam circuit edit. By doing so, the design specifications of high gain and low noise of the LNA are reliably met at high yield for the desired operating frequency. The presented DFFA method enables a shift in peak gain by 2.5 GHz. It thereby improves gain and noise figure at 24 GHz by 2 dB and -0.2 dB respectively. The resulting optimized LNA achieves a gain of 20 dB and a noise figure of 3.7 dB matching and surpassing other state-of-the-art works in a single prototyping run.

Fault isolation is an important initial component of the failure analysis investigation as it provides the first indicator of the defect physical location. The most broadly familiar fault isolation techniques include photoemission microscopy (PEM), optical beam induced resistance change (OBIRCH) and liquid crystal analysis (LCA). Each of these techniques has their own strengths but also drawbacks which can impede the analysis by either not providing a well isolated defect location or causing damage to the defect region. For some types of defects, photoemission and liquid crystal analysis may create local heating of the device which can distort the defect and mask the root cause of the failure. These techniques also rely on optical microscopy which has low resolution compared to the feature size of current technologies. In addition, each technique may not highlight the defect site itself; only pointing the analyst to the defective circuit within the sample. Electron Beam Induced Current (EBIC) and Electron Beam Absorbed Current (EBAC) microscopy provides solutions to these complications. In this paper we describe some very effective approaches by using these beam-based techniques in conjunction with traditional methods. As introduction, we have provided some interesting case studies whereby EBIC/EBAC have been used in conjunction with FIB circuit edits and scan diagnostic results to narrow the defect search areas. We focus the paper on some less common applications of cross sectional EBIC/EBAC as well as utilizing an AC coupled configuration to activate more subtle defect sites. We conclude with two examples where AC coupled cross-sectional EBIC is needed to highlight the cause of the failure.

Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

Shrinking transistor geometries present ongoing challenges for backside FIB circuit edit operations. The available space to gain access to critical signal lines has diminished to the order of hundreds of nanometers. Several previous works have shown that the diffusion of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon substrate is removed to less than 100nm, the effect can be seen electrically on a set of ring oscillators.

Despite commercial availability of a number of gas-enhanced chemical etches for faster removal of the material, there is still lack of understanding about how to take into account ion implantation and the structural damage by the primary ion beam during focused ion beam gas-assisted etching (FIB GAE). This paper describes the attempt to apply simplified beam reconstruction technique to characterize FIB GAE within single beam width and to evaluate the parameters critical for editing features with the dimensions close to the effective ion beam diameter. The approach is based on reverse-simulation methodology of ion beam current profile reconstruction. Enhancement of silicon dioxide etching with xenon difluoride precursor in xenon FIB with inductively coupled plasma ion source appears to be high and relatively uniform over the cross-section of the xenon beam, making xenon FIB potentially suitable platform for selective removal of materials in circuit edit application.

This paper offers an alternative solution in dealing with Focused Ion Beam (FIB) circuit edit debug of RF products that often required soldering the device onto a test board to enable sensitive RF characterization. Performing FIB circuit edit while the device is soldered on a test board not only eliminates signal degradation and inconsistency caused by a socket; but also, it allows for adding additional FIB edits on the same device. The conventional way of RF product debug of devices in a wire bond package was to characterize the device in a socket, perform the FIB circuit edit, encapsulate the cavity to protect the device from physical & thermal damage, solder the device onto the test board, and then perform post-FIB characterization. This is a very long, one-way process and needs multiple devices for design debug. For RF products in flip chip package, this approach was extremely difficult to almost impossible, because thermal stress of soldering device would significantly deform thinned die. All characterization had to be done with a socket, which often introduced changes of the same magnitude of the parameters of interest as well as repeatability issues. The purpose of this paper is to outline steps to allow for the RF FIB and characterization cycle to be done in a way to decrease throughput time and increase measurement accuracy. True characterization of highly sensitive RF circuit modifications is achieved through: soldering the device to the test board, performing sample preparation, preforming pre-FIB characterization, preforming FIB, and finally preforming post FIB characterization. Elimination of the need to solder a thinned device to a test board allows for the edit location to remain open enabling additional FIB edits to be performed on the same device. This eliminates redundant steps in the device sample preparation and enables quicker throughput times.