This paper presents a failure analysis to determine the origin of the failure on the soldered balls of one BGA soldered to a Printed circuit board, presenting Intermittency on the soldered joints, by Visual inspection, X ray inspection, Computed Tomography(CT), Cross-section analysis, Scanning Electron Microscopy, and Energy dispersive spectroscopy, determined the failure located on soldered balls of the BGA was caused by cracks that run along the Intermetallic layer formed between the solder balls and the copper pads of the printed circuit board, that were located near the BGA corners. With X ray computed Tomography we can analyze all the soldered balls of the BGA, by "virtual" cross-sections on the soldered joints without damage on the sample.

An advanced sample preparation protocol using Xe+ Plasma FIB for increasing FA throughput is proposed. We prepared cross-sections of 400 μm and wider in challenging samples such as a BGA (CSP), bond wires in mold compound or a TSV array. These often suffer from FIB milling artifacts. The unsatisfactory quality of the cross-section face is mainly due to extremely different milling rates of the various materials (polyimide, tin, copper, mold compound, platinum), ion beam induced ripples [1] or due to significant surface topography. We explored the usability of the protocol for standard cross-sections and also tested the preparation of TEM lamellae. The process parameters of the proposed approach were compared with the standard methods of Xe+ Plasma FIB FA with respect to preparation time and cross-section quality. Aiming for ultimate results, we incorporated the Rocking stage technique which also greatly improves cross-section quality.

Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

It is important to locate a short circuit failure in semiconductor devices, and powerful tools such as lock-in thermography and optical beam induced resistance change are used. However, those tools are inappropriate for investigating the device covered with the impenetrable substance to light, because the covering substance blocks the light from the defect point in the device and also prevents the optical beam from outside of the device. We demonstrate that a subsurface short circuit in a ball grid array device can be located by magnetic field imaging (MFI) and the electromagnetic field reconstruction method (EM-FRM), which makes it possible to calculate a magnetic field in the immediate vicinity of the current that is the source of the field from a measured magnetic field at a distance. Moreover, we visualize the short circuit by three-dimensional X-ray microscopy. MFI is also applied to visualization of a magnetic field created by a current flowing inside a printed circuit board and a light emitting diode package.

The X-ray inspection of fully assembled samples is becoming ever more important as the benefits of using area array packages/chip scale packages/flip chips are applied to more and more products. Sample preparation has traditionally been used to improve access to geometry or a specific location with a known defect that requires verification. The novel paradigm is an integrated approach to sample preparation and X-ray inspection to optimize resolution and throughput time performance with minimally deprocessed sample. This paper, covering the limitations of X-Ray imaging and 3D tomographic reconstruction, discusses the development of models for throughput time and resolution by failure analysis labs. It also discusses the processes involved in advanced sample preparation techniques and global BGA removal to obtain improved resolution at die level.

The continuous miniaturization trends followed by a vast majority of electronic applications results in always denser PCBs (Printed Circuit Board) designs and PCBAs (Printed Circuit Board Assembly) with increasing solder joint densities. Current high-end designs feature high layer count sequential build-up PCBs with fine lines/spaces and numerous stacked filled microvias, as well as closely spaced BGA/QFN components with pitches down to 0.4mm. In recent years, several 3D packaging approaches have emerged to further increase system integration by enabling the stacking of several dies or packages. This has translated for example into the advent of highly integrated complex System in Package (SiP) modules, Package-on-Package (PoP) assemblies or chips embedded in PCBs [1]. From a failure analysis (FA) perspective, this deep technology evolution is setting extreme challenges for accurately locating a failure site, especially when destructive techniques are not desired. The few conventional non-destructive techniques like optical or x-ray inspection are now practically becoming useless for high density PCB designs. This paper reviews several advanced analysis techniques that could be used to overcome these limitations. It will be shown through several examples how three non-destructive methods usually dedicated to package analyses can be efficiently adapted to PCBs and PCBAs: • Scanning Acoustic Microscopy (SAM) • 3D X-ray Computed Tomography (CT) • Infrared Thermography A case study of a flex-rigid board FA is presented to show the efficiency of these three techniques over classical techniques. In this example, not only the defect localization has been possible, but also the defect characterization without using destructive analysis.

A new approach to reliability improvement and failure analysis on ICs is introduced, involving a specifically developed tool for Topography and Deformation Measurement (TDM) under thermal stress conditions. Applications are presented including delamination risk or bad solderability assessment on BGAs during JEDEC type reflow cycles.

The development of a next generation high-resolution x-ray Computed Tomography (CT) tool and its applications are reported in this paper. Some of the key features are region of interest capability, improved time-to-data, improved usability, and data collection automation capability. We also discuss the key technical challenges that are faced by x-ray CT technology. Critical cases that are hard or not possible to isolate by alternative methods are also discussed. Examples include Controlled Collapse Chip Connection (C4) bump cracking and “invisible” non-wetting analysis, ball grid array (BGA) solder joint cracking, and wirebond microcracking and wirebond shorting, as well as demonstration of progressive testing capability.

The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

A packaged device based on a ball grid array or other design presents a challenge to the failure analyst. Accessing one of the metal levels from the topside requires decapsulation by either a wet, predominantly dry (RIE) or a completely dry (mechanical) treatment. To reveal the details of the gate including the gate oxide, new approaches to selective etch delineation by RIE are required. This article presents an automated sample preparation method for packaged microelectronic materials by combining plasma cleaning, ion beam etching, reactive ion etching and ion beam sputter coating. A single etch gas chemistry was effective in phase delineation by RIE. Future work to further delineate the gate oxides could support accurate metrology by means of FESEM rather than field emission transmission electron microscope.

Two instances of BGA package level failures were identified during in-circuit electrical test. The electrical opens occurred as a result of contamination issues originating at the board supplier. Analytical techniques including optical inspection, SEM/EDS, Raman and FTIR were key in identifying photoresist on the board surface in the first case study and nickel carbonate contamination on the board surface in the second case study. In the first case study, resolution was achieved with a Plasma etch process. In the second case study, CCAs were cleaned with a wet chemical etch process formulated specifically to attack the nickel carbonate.

Today's printed circuit assemblies comprise of several layers with components populated on both sides of the PCBs. This presents challenges to conventional 2D nondestructive X-ray techniques due to shadowing and absorption of the x-ray energy. Tilting of the samples while imaging helps to get around this problem, however, often it might not always be adequate. This article proposes a non-destructive method for detecting solder defects at the second level interconnect using 3D X-ray tomography. A total of 6084 solder joints of 0.8mm and 0.5mm pitch BGAs were analyzed. Correlation between dye stain and package pull analysis and 3D-uCT X-ray revealed a 100% correlation. Virtual cross sections obtained using 3D x-ray tomography methods showed that it is possible to evaluate non-destructively the solder joint failure mode "H" known as "head-pillow or snowman" at the second level interconnect.

The demand for shifting from lead-containing to lead-free solder materials as well as the ongoing efforts for an improvement of the solder joint robustness for fine-pitch ball grid array packages requires ongoing testing of fresh solder alloys, changes in landing pad metallization and reflow processes. This testing includes mechanical and thermal stress tests and a detailed failure and material analysis. Besides the commonly used analysis methods like optical microscopy, scanning electron microscope (SEM) imaging of cross sections, fracture planes and energy dispersive X-ray compositional analyses, other techniques such as ion channeling contrast and transmission electron microscope (TEM) imaging can provide valuable information on intermetallic compounds (IMC) formation at solder joint interfaces. This paper discusses the advantages of SEM imaging of IMC morphology at the pad interface resulting from solder ball etching, focused ion beam imaging of solder ball cross sections with ion channeling contrast, and TEM analyses of failures.

During the last few years the drop test has become more and more important for electronic handheld components. Drop test reliability for lead-free solder interconnects is an extreme challenge today. Thus, the need for improved micro structural diagnostics of new material combinations and crack detection methods has increased. The target of this paper is to summarize detection and analysis methods for solder joint cracks, material characterization [1] and preparation methods of assembled printed circuit boards (PCB) after a drop test to completely understand lead-free solder interconnect reliability in fine pitch ball grid array packages (FBGA). In particular, we will introduce the outstanding advantages of embedded cross-sections combined with ion beam polishing (IBP), dye- or rather resin-penetration, selective tin etch and micro-hardness measurements.

The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Acoustic Micro Imaging (AMI) is an established nondestructive technique for evaluation of electronic packages. Non-destructive evaluation of electronic packages is often a critical first step in the Failure Analysis (FA) process of semiconductor devices [1]. The molding compound to die surface interface of the Plastic Ball Grid Array (PBGA) and Plastic Quad Flat Pack (PQFP) packages is an important interface to acquire for the FA process. Occasionally, with these packages, the standard acoustic microscopy technique fails to identify defects at the molding compound to die surface interface. The hard to identify defects are found at the edge of the die next to the bond pads or under the bonds wires. This paper will present a technique, Backside Acoustic Micro Imaging (BAMI) analysis, which can better resolve the molding compound to die surface interface at the die edge by sending the acoustic signal through the backside of the PBGA and PQFP packages.

In time domain reflectometry (TDR), the main emphasis lies on the reflected waveform. Poor probing contact is one of the common problems in getting an accurate waveform. TDR probe normalization is essential before measuring any TDR waveforms. The advantages of normalization include removal of test setup errors in the original test pulse and the establishment of a measurement reference plane. This article presents two case histories. The first case is about a Plastic Ball Grid Array package consisting of 352 solder balls where the open failure mode was encountered at various terminals after reliability assessment. In the second, a three-digit display LED suspected of an electrical short failure was analyzed using TDR as a fault isolation tool. TDR has been successfully used to perform non-destructive fault isolation in assisting the routine failure analysis of open and short failure. It is shown to be accurate and reduces the time needed to identify fault locations.

This paper describes a novel approach for safe handling of the thinned die from the front; a technique that can also be successfully applied to preserve cracked die. The discussion provides details on the characteristics and processes involved in backside reconstruction, thinned die reconstruction, and front-side deprocessing of thinned die. The finished backside reconstruction sample was cross-sectioned for examination using a diamond saw. After 6 hours of bake, no cracking of the thinned die was observed. Front-side deprocessing was then applied to the backside reconstructed sample. The sample remains intact. The technique has proven to be easily applied and highly reliable, and provides a solution for front-side deprocessing for both high pin count ball grid arrays and flip chips.

A new generation X-ray laminography (XRL) automated Xray inspection (AXI) tool was evaluated for surface mount technology (SMT) assembly defect detection and was qualified using formal “benchmark” comparative analysis processes. In addition, defect characterization was performed using the XRL AXI system in manual X-ray inspection mode to correlate various failure modes and mechanisms at SMT solder joint interfaces for selected non-destructive failure analyses and technology development. Since ball grid array (BGA) solder joint quality is a great concern in board assembly, test technology development and failure analysis teams explored the use of XRL AXI as a method to detect and monitor BGA ball abnormalities using XRL AXI-generated solder ball images and measurements. It was found that XRL AXI was able to successfully discern differences in the shape, location and diameter of the suspect BGA solder balls from XRL AXI horizontal image planes (slices) for physical failure analysis and reliability issues not previously detected using conventional X-ray transmission or electrical methods. Subsequent metallographic x-sectioning correlated the XRL AXI mages to the physical condition of the suspected second level interconnect (SLI) solder joint location.