Given the challenges FA Engineers have in fault localization, top-side analysis is facing a major challenge with today’s advanced packaging and shrinking of die sizes. At wafer and die level it is relatively easy to probe with little or no sample preparation. Greater challenges occur after the die is packaged. The difficulty further lies in non-destructively analyzing the die. Another issue with failure analysis is accurately deprocessing the device for probe pad deposition. Techniques like Electro Optical Probing (EOP) or Laser Voltage Probing (LVP) acquire electrical signals on transistors and create an activity map of the circuitry. In failure analysis, it is applied to localize defects. This paper discusses integrating EOP techniques in traditional FA to localize failure in mixed signal ICs. Three case studies were presented in this paper to establish the technique to be effective, quick and easy to probe non-invasively with minimal backside sample preparation.

We present a characterization methodology for fast direct measurement of the charge accumulated on Floating Gate (FG) transistors of Flash EEPROM cells. Using a Scanning Electron Microscope (SEM) in Passive Voltage Contrast (PVC) mode we were able to distinguish between '0' and '1' bit values stored in each memory cell. Moreover, it was possible to characterize the remaining charge on the FG; thus making this technique valuable for Failure Analysis applications for data retention measurements in Flash EEPROM. The technique is at least two orders of magnitude faster than state-of-the-art Scanning Probe Microscopy (SPM) methods. Only a relatively simple backside sample preparation is necessary for accessing the FG of memory transistors. The technique presented was successfully implemented on a 0.35 μm technology node microcontroller and a 0.21 μm smart card integrated circuit. We also show the ease of such technique to cover all cells of a memory (using intrinsic features of SEM) and to automate memory cells characterization using standard image processing technique.

Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require backside sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces will typically use conventional Laser Chemical Etching (LCE) platforms. The focus of this analysis will be to investigate and conjoin previously published techniques to this local preparation by using a combination of laser sources. A Continuous Wave (CW) and Pulse laser will be used at various processing stages to de-process IC packaging materials silicon and mold compound encapsulation.

Post silicon validation techniques on Integrated Circuits (IC) specifically FIB circuit editing require backside sample preparation done by local mold compound and silicon machining. Conventional methods such as Computer Numerically Controlled (CNC) machining and chemical etching preparation platforms are commonly used. This paper will investigate a simple alternative approach to local sample preparation by using micro-abrasive blasting. This approach will display its simple natured set-up along with extremely quick process duration.

Backside sample preparation is required by many post silicon validation techniques like FIB (Focused Ion Beam) circuit editing and optical probing using Photon Emission or Laser Stimulus methods [1]. In spite of many conventional methods of silicon thinning and polishing, some challenges remain as new packages are introduced. With large die packages the issue of cracking during backside thinning is arising due to package curvature stress. 3D profile methods will be shown in conjunction with thermal relaxation to alleviate silicon center to edge variance allowing sample prep of large areas with thicknesses below 10μm. Thinning and polishing methods will be shown to be interactive with the device heated; demonstrating both thermal stress reduction coupled with curvature reduction.

Post silicon validation techniques require backside sample preparation by silicon thinning techniques. The conventional fixture to this preparation on large die packages causes silicon to crack. A new “4-point bending” fixture was developed to reduce silicon bending strain during thinning to eliminate silicon cracking. This new fixture and technique improved remaining silicon thickness uniformity as well as process time.

Ultra-short pulse laser ablation is applied to IC backside sample preparation. It is contact-less, non-thermal, precise and can ablate the various types of material present in IC packages. This study concerns the optimization of ultra-short pulse laser ablation for silicon thinning. Uncontrolled silicon roughness and poor uniformity of the laser thinned cavity needed to be tackled. Special care is taken to minimize the silicon RMS roughness to less than 1µm. Application to sample preparation of 256Mbit devices is presented.

With technology scaling down to sub 0.16um and metalization exceeding 7 levels, the development of reproducible backside silicon sample preparation techniques becomes increasingly important to accurately localize defects. Bulk silicon thinning is a critical step in the backside sample preparation process. This paper will discuss two different ways for silicon thinning: reactive ion etching (RIE) alone, and RIE in conjunction with mechanical milling. In addition, the characterization and optimization of the RIE process for backside silicon thinning will be discussed in this paper. We have found mechanical milling works well for many package types; however, we have had difficulty reproducibly thinning certain package types such as very small die or packages where the wire bonds are in the plane of the silicon die and are in very close proximity to the edge of the die. In these cases, we have found that reactive ion etching (RIE) can be used successfully. We have also found that for package types where mechanical milling works, the combination of mechanical milling and reactive ion etching process is a useful technique for accurately controlling the final thickness of the silicon. This technique combines the speed of mechanically milling and the advantage of RIE process to accurately control the etch rate and etch process in the final stages of thinning the silicon die.

An increasing number of analysis techniques requires access to the backside silicon of a functional device. For backside sample preparation of packaged devices, CNC milling tools can perform both package opening and circuit preparation. They offer good versatility in terms of type and size of packages – from ceramic to exotic plastic molding. They are suited for precise silicon thinning as well as polishing. Finally, the automation and software control of the process offer good reproducibility of chip opening and preparation. For some applications, the silicon substrate needs to be thinned as closely as possible to the circuitry with a uniform thickness (less than 100 microns). Bent silicon surfaces are challenging for backside sample preparation. This is the case of C4 packages or large plastic TSOP packages. Conventional approaches would cut off the top of the bent surface. From small flat surface to large bent silicon dies, we will detail our technique for thinning silicon to a uniform thickness with extreme precision. Finally, we will characterize the final surface roughness which plays an important role in backside techniques.

This paper presents a comparative study of backside sample preparation techniques with applicability to conventional as well as flip chip package types. We will cover mechanical (grinding and milling tools), chemical (wet and dry chemistries) and other approaches such as laser ablation. Backside sample preparation is very challenging. The preparation process flow starts with decapsulation of the ceramic or plastic package, continues with the die paddle removal, silicon thinning and finishes with silicon polishing. The techniques involved include mechanical, chemical and other novel approaches for ceramic and plastic package. Today, only CNC milling can cover the whole process for almost any kind of packages. Nevertheless, photo ablation is a rising technology for package decapsulation. In addition, chemical wet etch can be used to perform silicon thinning and polishing. We will illustrate the complexity of the process through examples. The first one is a ceramic package where the main issue is the hardness of ceramic. The second one is a TSOP package where the main challenge is the chip scaled package. Both will be observed through the IR emission microscope to demonstrate the efficiency of the preparation.

A new ultra-short pulse laser ablation based backside sample preparation method has been developed. This technique is contact-less, non-thermal, precise, repetitive and adapted to each type of material present in IC packages. Backside preparation examples are presented on a conventional DIL plastic package, on a TSOP plastic package with an oversized silicon die, on a DIL ceramic package and on a CCD device. Feasibility of silicon thinning using laser ablation is also discussed.