In-line e-beam inspection is performed to detect dark voltage contrast (DVC) defects on normally bright W-plugs. Cross-sectional SEM and TEM in an FA lab verified that the different gray level values (GLV) of DVC defects are caused by different resistances of the W-plugs. We found that DVC defects with lower GLV (GLV1) are W-plugs that are open and almost open. DVC defects with GLV2 are caused by partially open W-plugs and in-plug voids.

Analog Devices General Trias (ADGT) received a challenging customer return unit (CRU) for failure analysis (FA). The CRU is a frequency synthesizer failing to lock at the customer’s application frequency at cold temperature condition. The failure has been simulated during bench testing at the ADGT FA laboratory at ambient temperature with VDD supply voltage lowered to 2.38V from nominal value of 3.0V. Series of fault isolation analyses using Light Emission Microscopy (LEM) and Optical Beam Induced Resistance Change (OBIRCH) localized the failure to a bipolar transistor (NPN) in the feedback divider block of the frequency synthesizer. Circuit level spice simulation replicated the functionality failure when a 2.6K-ohms resistance is connected to the emitter of the transistor. Physical failure and elemental analyses found traces of native oxide in the Nitrogen (N2) rich Titanium Nitride (TiN) layer between the Tungsten (W) plug and Titanium (Ti) liner in the emitter plug of the failing transistor. The oxide interface acts as a barrier to the flow of charge carriers in the emitter leading to the temperature dependency failure; failing at cold temperature and passing at ambient temperature. Corrective actions have been put in-place as a result of the successful identification of the defect.

Possible reliability failure mechanisms on mixed-signal IC are reviewed and categorized. Based on the nature of reliability and low DPPM failures on mixed signal IC, an analysis flow is proposed including identification of individual failure mechanisms, extraction of the systematic problems, and implementation of corrective actions. Finally, a case of successful isolation of a specific defect without common electrical signature on mixed-signal devices is presented.

High contact resistance can be caused by moisture absorption in low phosphorus content BPTEOS. Moisture diffused through the TiN glue layer is absorbed by the BPTEOS during subsequent thermal processes resulting in increased contact resistance. This failure mode was studied by combining different failure analysis methods and was confirmed by duplication on experimental wafers.

In this paper, a novel inspection mode of electron beam inspection (EBI) that can effectively detect buried voids in tungsten (W) plugs is reported for the first time. Buried voids in metal are a defect of interest (DOI) that cannot be captured by either optical inspection or traditional EBI modes. The detection of buried voids is achieved by using energetic electron beam (e-beam) with energy high enough to penetrate into metal and reach the buried void. By selecting desired secondary electrons to form the inspection images, strong contrast between the defective tungsten plugs and normal ones can be achieved. Failure analysis was performed on the DOI that is unique to this new EBI mode. After optical microscope locating and laser marking, we successfully recaptured DOI with scanning electron microscope (SEM) and capped the DOI with e-beam assisted platinum (Pt) deposition. Later a dual-beam focused ion beam (FIB) system was used to re-locate the Pt-capped DOI and prepare samples for transmission electron microscope (TEM). TEM images confirmed the unique DOI were buried voids in the metal plugs, which could affect resistance of interconnect in integrated circuit (IC) chip and impact the IC yield.

A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Smaller technologies and increasing chip functionality has resulted in tightly packed devices and more stacked metal layers. For technologies between 0.25µm and 0.14 µm, stacking packed metal layers required the combination of Tungsten plugs as interconnection and the utilization of Chemical Mechanical Polishing (CMP). “Pillar”, however, is a small metal line, which allows interlevel connections between Tungsten plugs. The size and shape of the pillar can be a yield limiting issue. The process of identification and resolution of the missing metal pillar included yield analysis, electrical and physical failure analysis, root cause analysis and the engineering coordination of photo engineering, etch process engineering, CMP engineering, integration engineering, and inline inspection. Resolving the missing pillar issue has proven to have significant contribution to yield.

To find defects and their root cause in semiconductor devices has become more and more difficult as chip size dramatically drops. A novel method combining FIB sequential cross-sectioning and TEM is described in this paper. This combination has provided a powerful tool for defect mechanism analysis. FIB slicing through a failed cell can be controlled to a precision of 0.1 micron. Passive voltage contrast imaging with FIB enhances defect detection. After a defect is found, in-situ TEM sample is prepared with FIB milling. By putting together the series FIB images along side with the TEM images and its associated high resolution EDS data, the detailed defect formation mechanism was discovered and feedback to process engineering for process improvement.

Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

For a certain class of defects substantial time has to be invested to be able to pinpoint the exact electrical failure location and to perform an accurate and conclusive physical characterization. This article shows that 3D scanning transmission electron microscopy (STEM) tomography in conjunction with an original sample preparation method is a valuable technique to tackle this class of defects and that it can provide very accurate and useful information on these defects. The developed method is applied to analyze several failing devices that are all designed with 45nm design rules and fabricated using a 45 nm technology, and is illustrated with 3 different case studies, each referring to one fault localization method. It is concluded that 3D STEM tomography can provide conclusive 3-dimensional analytical and morphological information on the localized defect, provided that special care is taken to prepare a well-adapted sample.

The identification of foreign material at metal-oxide interface or at the poly-substrate interface by means energy dispersive spectroscopy (EDS) is very difficult. Auger depth profiling can be used as an alternative method to cross-section EDS analysis for the identification of very thin layers of foreign material in semiconductor devices. This article presents a sample preparation method adapted from a planar transmission electron microscopy sample preparation method so that Auger depth profiling can be used as a practical tool for identifying very thin layers of foreign materials at interfaces buried deep within semiconductor devices. The discussion covers the advantages, applications, and the procedure for performing the analysis. The high degree of control provided by the method gives an analyst the ability to easily thin down material layers to less than 100nm of a target layer, thereby significantly reducing sample preparation time as well as analysis time on the Auger tool.

Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.

A single bit failure is the most common and the most difficult failure mode to analyze in a Static Random Access Memory (SRAM). As chip feature sizes decrease, the difficulties compound. Traditional failure analysis techniques are often ineffective, particularly for high temperature operating life (HTOL) failures, because HTOL failures are most often caused by subtle physical defects. A new analysis approach, using Focused Ion Beam (FIB) cross-sectioning combined with FIB passive voltage contrast (PVC), greatly enhances the analysis success rate. In this paper, we outline the use of these new techniques and apply them to a technologically important problem.

Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.

Electron-Beam Induced Resistance CHange (EBIRCH) is a technique that makes use of the electron beam of a scanning electron microscope for defect localization. The beam has an effect on the sample, and the resistance changes resulting from that effect are mapped in the system. This paper explores the beam-based nature of the technique and uses understanding from another beam-based technique, Optical Beam Induced Resistance CHange (OBIRCH), to propose a dominant mechanism. This mechanism may explain the widely different success rates between different types of samples observed after six month’s use of the technique for isolations on large health of line structures in a failure analysis lab.

Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

This paper introduces a technique to reveal a small feature defect of an SRAM cell via utilizing a 200kV dedicated field emission STEM on a FIB prepared sample. The initial TEM sample contains the entire defective cell; one side of the sample has n-type transistors and the other p-type. Both sides of the sample were observed using STEM bright field and dark field (HAADF) detectors (transmitted beam – inner information) and SEM mode (surface and sub-surface information). With deep beam penetration of STEM, one contact was found to be very close to the poly gate. Further FIB cuts were performed to remove the rest of the bulk away from the defect, thinning down to the area of interest. When the sample was thinned to a final thickness of less than ~100nm, a final image was taken of the exposed defect. The failing root cause was that the upper corner of the poly had touched the adjacent contact. Such an approach offers many unique advantages for site specific failure analysis over conventional SEM and/or TEM techniques.

Identifying defects in marginally failed vias has long been a challenge for failure analysis (FA) of state-of-the-art semiconductor integrated circuits. This paper presents two cases where a conventional FA approach is found to not be effective. The first case involves high resistance or marginally open vias. The second case involves early breakdown of large capacitors. The large size of the capacitor and the lack of ways to track electrical flow during diagnosis made it difficult to isolate the defect. The paper shows that conducting atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) are effective techniques for isolation of via-related defects. The SCM technique could be applied to samples without a direct conducting path to the substrate, such as SOI samples. On the other hand, C-AFM allows current imaging as well as I-V characterization whenever a direct conductive path is available.

Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.