Recent developments in transmission electron microscopy (TEM) sample preparation have greatly reduced the time and cost for preparing thin samples. In this paper, a method is demonstrated for viewing thin samples in transmission in an unmodified scanning electron microscope (SEM) using an easily constructed sample holder. Although not a substitute for true TEM analysis, this method allows for spatial resolution that is superior to typical SEM imaging and provides image contrast from material structure that is typical of TEM images. Furthermore, the method can produce extremely high resolution x-ray maps that are typically produced only by scanning transmission electron microscope (STEM) systems.

Forming and breaking a nanometer-sized conductive area are commonly accepted as the physical phenomenon involved in the switching mechanism of oxide resistive random access memories (OxRRAM). This study investigates a state-of-the-art OxRRAM device by in-situ transmission electron microscopy (TEM). Combining high spatial resolution obtained with a very small probe scanned over the area of interest of the sample and chemical analyses with electron energy loss spectroscopy, the local chemical state of the device can be compared before and after applying an electrical bias. This in-situ approach allows simultaneous TEM observation and memory cell operation. After the in-situ forming, a filamentary migration of titanium within the dielectric hafnium dioxide layer has been evidenced. This migration may be at the origin of the conductive path responsible for the low and high resistive states of the memory.

Transmission electron microscopy (TEM) [1] and scanning capacitance microscopy (SCM) [2] have become common failure analysis tools at Sandia for new product development, process validation, and yield enhancement. These two techniques provide information that cannot be obtained with other analytical techniques. The information provided by these two techniques has been instrumental in identifying the root causes of several yield-limiting defects in CMOS IC technologies at Sandia. This paper describes an example of how TEM and SCM have been used to identify the root causes of SOI device failures. The corrective actions taken to reduce defects and improve yield are also described.

By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.

Presentation slides for the ISTFA 2024 Tutorial session “Transmission Electron Microscopy.”

Atom probe tomography is used to characterize the 3D Al dopant distribution within the gate diffusion region of a deconstructed SiC n-channel junction field effect transistor. The data reveals extensive inhomogeneities in the dopant distribution, which manifests as large Al clusters - some of which are ring-shaped and indicative of dopant segregation to lattice defects in the SiC. The presence of defects in the SiC is confirmed by transmission electron microscopy of an identical region. Factors that may impact the atom probe data quality and consequently complicate data interpretation are considered, and their severity evaluated. The possible origin of the lattice defects in the SiC and the corresponding implications for device performance and reliability are also discussed. Overall, the utility of atom probe tomography and correlative transmission electron microscopy for revealing potential failure mechanisms of next-generation semiconductor devices is demonstrated.

Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.

The specimen preparation technique using focused ion beam (FIB) to generate cross-sectional transmission electron microscopy (XTEM) samples of chemical vapor deposition (CVD) of Tungsten-plug (W-plug) and Tungsten Silicides (WSi x ) was studied. Using the combination method including two axes tilting[l], gas enhanced focused ion beam milling[2] and sacrificial metal coating on both sides of electron transmission membrane[3], it was possible to prepare a sample with minimal thickness (less than 1000 A) to get high spatial resolution in TEM observation. Based on this novel thinning technique, some applications such as XTEM observation of W-plug with different aspect ratio (I - 6), and the grain structure of CVD W-plug and CVD WSi x were done. Also the problems and artifacts of XTEM sample preparation of high Z-factor material such as CVD W-plug and CVD WSi x were given and the ways to avoid or minimize them were suggested.

In this study, the interface reactions between eutectic SnPb solder and two Ni-based UBM systems are reported, namely the sputtered Cu/Ni(V)/Al and the electroless Au/Ni(P) systems. Comparisons are made to the conventional Au/Al ball bonding system in terms of microstructure evolution, and metallurgical stability. TEM sample preparation is critical in this analysis. The capability of TEM in UBM microstructure studies is demonstrated.

In this work, we investigate mushroom type phase-change material (PCM) memory cells based on Ge 2 Sb 2 Te 5 . We use low-angle annular dark field (LAADF) STEM imaging and energy dispersive X-ray spectroscopy (EDX) to study changes in microstructure and elemental distributions in the PCM cells before and after SET and RESET conditions. We describe the microscope settings required to reveal the amorphous dome in the RESET state and present an application example involving the failure analysis of a PCM test array made with devices fabricated at IBM’s Albany AI Hardware Research Center.

In this article, an analysis of a failure in the embedded SRAM in a CMOS Image Sensor is investigated. The failure was due to unformed CoSi2. Because unformed CoSi2 causes a varying degree of response, a nano-prober was used to find the abnormally operating transistors among a 1-bit SRAM cell consisting of six transistors(6T). After measuring and analyzing the current-voltage relationships between each transistor, the current magnitude of one pull-down transistor was found to be less than the expected range and particularly lower than that of a connected access transistor. To visualize the failure phenomenon and find the root cause of this, TEM analysis was conducted. Using the EELS (Electron Energy Loss Spectroscopy) elemental mapping, unformed CoSi2 was detected between the contact and substrate, where the contact corresponds to the VSS of the pull-down transistor. This caused an increase in the contact resistance, thus lowering the current magnitude of the abnormal transistor to a greater degree than expected.

The endurance performance of a novel confined phase change memory cell with metallic nitride liner is investigated using a transmission electron microscope (TEM). Write endurance has been shown to be substantially improved by this new structure [1]. Memory cells that had been cycled up to 10 9 were cross-sectioned and studied using the TEM. A majority of the electrically observed endurance failure mechanisms were stuck-SET. Physical failure analysis showed the failed cell is always associated with large void formation and material segregation. In-situ TEM analysis was used to study the void formation, accumulation and movement, where the memory cell was simultaneously operated and imaged in the TEM. Also, an interesting self-healing process of the void was recorded during the set/reset operation.

In this paper, a sample was made on an advanced technology node finFET test structure and analyzed in a 200kV TEM equipped with a 4k camera and commercially available strain analysis software using a sub 5nm parallel probe. It was observed that doubling the step size of the data acquisition from 5nm per step to 2.5nm per step with a 4k image resolution changed the sensitivity of the data by about 4%. However, increasing the number of pixels of each diffraction pattern from 2k to 4k and removing the focused ion beam prepared sample surface damage both showed greater than 10% improvements in nano beam electron diffraction (NBD) sensitivity greater than 10%. As a result, it is possible to obtain greater sensitivity of the NBD technique by employing these changes in response to the evolving characterization needs.

Transmission electron microscopy (TEM) sample can be routinely made at a sub 30nm thickness and specific features in semiconductor device design are on the order of 30nm and smaller. As a result, small changes in pattern match registration can significantly influence the success or failure of proper TEM sample placement as an approximately 15nm shift in lamella placement can easily cause the sample to be off the feature of interest. To address this issue, design based recipe writing is being developed on a dual beam focused ion beam platform. The intent is to have the tool read a GDS file and pattern match the design information to physical wafer images in a similar fashion to state-of-the-art critical dimension scanning electron microscopy operation. While the results are very encouraging, more work needs to be done to ensure a TEM sample of approximately 30nm thickness is placed at the desired location.

The capabilities of analytical transmission electron microscopy (TEM), such as high spatial resolution, micro-chemical analysis, etc., have led to an increasingly essential role for TEM-based analysis in process development, defect identification, yield enhancement, and root-cause failure analysis with the dynamic random access memory (DRAM) industry. In this article, several examples are reported to carry out the applications of TEM and secondary ion mass spectrometry on crystal defect analysis and electronic characteristics of advanced 512 Mb DRAMs.

The aggressive scaling of metal oxide semiconductor field effect transistor (MOSFET) device features, including gate dielectrics, silicides, and strained Si channels, presents unique metrology and characterization challenges to control electrical properties such as reliability and leakage current. This paper describes challenges faced in measuring the thickness of thin gate oxides and interfacial layers found in high-K gate dielectrics, determining Ni silicide phase in devices, and characterizing strain in MOSFETs with SiGe stressors. From case studies, it has been observed that thin layers (gate oxide, high-K film thickness, and interfacial layer) can be measured using high-resolution transmission electron microscopy (HRTEM) with good accuracy but there are some challenges in the form of sample thickness, damage-free samples, and precise sectioning of the sample for site-specific specimens. Complementary information based on HRTEM, annular dark field, and image simulation should be used to check the accuracy of thin gate dielectric measurements.

Since strain engineering plays a key role in semiconductor technology development, a reliable and reproducible technique to measure local strain in devices is necessary for process development and failure analysis. In this paper, geometric phase analysis of high angle annular dark field - scanning transmission electron microscope images is presented as an effective technique to measure local strains in the current node of Si based transistors.

Imaging tomography by transmission electron microscopy (TEM) is a technique which has been growing in popularity in recent years, yet it has not been widely applied to semiconductor defect studies and root cause determination [1- 3]. In part this is due to the complex equipment, computing needs, and microscope time required to generate the various images which ultimately compose the data set. However, the latest generation of TEMs—with their high level of stability and automation—are greatly reducing the resource needs to create high quality and informative movies of defects rotating about a central axis. One significant advance is the reduction in time required to fabricate a sample and perform the data acquisition by TEM. Today’s microscopes allow for sample fabrication to take place in a few hours or less and can acquire more than 100 images in about an hour at different sample tilt conditions with minimal analyst intervention. This paper describes using automated TEM sample preparation with dual beam focused ion beams (previously reported [4]) in conjunction with automated tomography software on a state-of-the-art TEM. By using an advanced tomography holder ±70° of tilt can be obtained. This is a powerful way to view defects as the failure can be viewed through more than 90° of rotation. Consequently a more complete understanding of the failure site can be obtained over a typical single projection TEM image. This can greatly facilitate root cause determination in a timely manner.

For 22nm technology node and beyond, fully depleted devices such as FinFET and ETSOI are leading candidates. Certain critical dimensions of such devices are well below 10nm, and only transmission electron microscopy (TEM) has the resolution to provide measurement with sub-nanometer accuracy. Due to the projection effect of TEM technique, comprehensive understanding of the 3D structure from 2D images is needed for process development of FinFET. This paper will address sample preparations and TEM imaging techniques for FinFET device at sub-100nm pitch.

Different epitaxial structures have been studied by high-resolution x-ray diffraction and x-ray topography, Transmission Electron Microscopy and Atomic Force Microscopy to establish correlations between epitaxial growth conditions and crystal perfection. It was confirmed that epitaxial growth under initial elastic stress inevitably leads to the creation of extended crystal defects like dislocation loops and edge dislocations in the volume of epitaxial structures, which strongly affect crystal perfection and physical properties of future devices. It was found that the type of created defects, their density and spatial distribution strongly depended on growth conditions: the value and sign of the initial elastic strain, the elastic constants of solid solutions, the temperature of deposition and growth rate, and the thickness of the epitaxial layers. All of the investigated structures were classified by their crystal perfection, using the volume density of extended defects as a parameter. It was found that the accommodation and relaxation of initial elastic stress and creation of crystal defect were up to four stages “chain” processes, necessary to stabilize the crystal structure at a level corresponding to the deterioration power of particular growth conditions.