1-20 of 90 Search Results for

transition delay faults

Follow your search
Access your saved searches in your account

Would you like to receive an alert when new items match your search?
Close Modal
Sort by
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 369-376, October 31–November 4, 2021,
...Abstract Abstract This paper presents a user-defined fault model (UDFM) that accounts for silicon behaviors that cannot be explained using traditional stuck-at and transition delay fault models. The new model targets cell-internal faults but does not require time-intensive SPICE simulations...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 196-200, November 5–9, 2017,
... test, specifically a Transition Delay Fault (TDF) pattern. A TDF pattern is an at-speed test which can either be a slow-to-rise or a slow-to-fall fail [7]. The diagnostics on this device gave poor results and had multiple suspects spread across an area of 100 s of microns, calling out multiple cells...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 419-425, November 10–14, 2019,
...-at, transition delay, cell aware, and IDDQ. A pattern could be written out for each of this fault models. The effectiveness of a certain pattern to cover these faults could be summarized in a report. An example of this report is shown in Figure 1. The total number of faults, different fault classes...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 148-153, November 10–14, 2019,
... package was returned from a customer. The returned unit was noted to pass all Stuck-at Scan test patterns and fail only transitional delay fault scan patterns. Using a bench top digital tester, a known good unit was noted to pass all transitional delay patterns down to 0.8x TSF (TSF = Time Scaling Factor...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 532-537, November 11–15, 2012,
... periods. Various delay fault models have been developed to guide the generation of delay-based test vectors. The most widely-used models include the transition delay fault (TDF) model, and the path delay fault (PDF) model. The TDF model targets each gate output for a slow-to-rise and slow-to-fall delay...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 93-103, October 28–November 1, 2018,
... performance offered this simply adds addition delay. This limitation is efficiently addressed with the implementation of LIFA. With LIFA enabled to spatially map all the FFs residing after the stuck-at fault, only a single scan of the FOV returns a striking result that contains excellent SNR and best-in-class...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 436-445, November 9–13, 2014,
... techniques, followed through by data analysis, and constantly building knowledge and expertise. The first case showed that an effective approach for performing dynamic fault localization using an at-speed test like transition delay can be achieved by combination of a compact and low noise test system...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 383-389, November 2–6, 2008,
..., it generates 2-cycle transition delay test patterns and propagates the fault effects to primary outputs and scan cells for failure observation. Chip Failed Scan Test Fail log collection Logic Diagnosis Physical Fault Isolation Debug-Oriented Test Patterns Physical Failure Analysis Figure 1: Silicon debug flow...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 396-401, November 2–6, 2008,
... works with both (0Æ1) transitions and (1Æ0) transitions for faults that fail at both low and high Vdd. 0 1 1 0 0 1 1a(i+6) a(i+7) a(i+7) 0 0 1/0 1 0/1 0 1 Step2: Bump the Voltage condition and one cycle shift to cause the hold time faults. =>Change the Voltage condition to non- working condition...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 345-351, November 15–19, 2020,
... to support multiple faults in [11]. Signal profiling was proposed to diagnose chain failures in [12]. [13] formulated hold-time diagnosis as a delay insertion process, and called out the cell with the best alignment. In [14], a new algorithm was proposed to diagnose all types of chain faults based...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 103-111, November 13–17, 2011,
... of such clock defects and propose an algorithm to diagnose it. clock defects clock tree computer algorithm defective clock signal hold time faults scan testing spot delay defects Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree Yu Huang, Wu-Tung Cheng, Ting-Pu Tai...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 171-175, November 5–9, 2017,
... known as a stuck-at failure. Enhancements to the technique are required when the chain has transition failures or corruption to the duty cycle. Conventionally, LVP is used for these type of failures which increases the time taken for finding the fault as this involves probing the individual transistors...
Proceedings Papers

ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 483-488, November 15–19, 1998,
... and 13 is significantly less than, for example, the 382 psec delay between inverters 5 and 9, showing the effect of the pre-charging. Half a cycle of the ring later, when the opposite transitions are occuring, the resistor acts as an additional load when the output of inverter 10 is going low. This extra...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 528-532, November 9–13, 2014,
.... Increasing clock frequencies and smaller design features have led to the development of more exotic fault models and test strategies. It is typical for a modern SOC to employ numerous ATPG fault models in a given test solution. These include traditional Stuck-At, Transition Fault, Path Delay, and more...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 336-340, November 3–7, 2013,
...: 10.31399/asm.cp.istfa2013p0336 Copyright © 2013 ASM International® All rights reserved. www.asminternational.org Chip Description In summary, we created four families of experiments: individual devices, simple delay chains with dedicated inputs, some of which are configurable into ring oscillators, larger...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 12-17, November 13–17, 2011,
... at both data and clock frequencies did not reveal any anomalies. A modulation map at the 2 nd harmonic of the data frequency of the last flop (C00000) revealed that the output was a transition fault: data patterns changing from 11001100 to 10001000 Probing of the Q output of C00000 confirmed...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 82-86, November 9–13, 2014,
... at one of the passing sites to temporally localize the fault, which is indicated by the trailing, rising edge of in the TR-LADA waveform. The timing was used to set the delay for LVP analysis, which revealed a 150ps glitch in the clock signal. Visualizing the direction of signal propagation...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 84-95, October 31–November 4, 2021,
... as input for DALS analysis. The approach used for a successful DALS analysis of each case will be discussed in detail . Introduction SDL has been proven to be an effective fault localization technique utilized for soft defect types of failures. Soft defects are failures that are failing at some...
Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 384-388, November 14–18, 2010,
... measurement loop. In order to be used for emission measurement, debug friendly transition delay test patterns [12] should be generated. A link to a pattern conversion tool allows a quick transfer of the generated test pattern to the used tester platform. Spice Net List Extraction for Simulation After...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 52-57, November 14–18, 2004,
... diagnosis and delay fault coverage , Proc. NATW, 2000, pp. 14-18. [4] K. Stanley, High accuracy fault and scan software diagnostic , Workshop on Field Optimization & Test, 2000. [5] F. Stellari, P. Song, J.C. Tsang, M.K. McManus and M.B. Ketchen, Circuit voltage probe based on time-integrated measurements...