A failure analysis application utilizing scanning acoustic microscopy (SAM) and time domain reflectometry (TDR) for failure analysis has been developed to isolate broken stitch bonds in thin shrink small outline package (TSSOP) devices. Open circuit failures have occurred in this package due to excessive bending of the leads during assembly. The tools and their specific application to this technique as well as the limitations of C-SAM, TDR and radiographic analyses are discussed. By coupling C-SAM and TDR, a failure analyst can confidently determine whether the cause of an open circuit in a TSSOP package is located at the stitch bond. The root cause of the failure was determined to be abnormal mechanical stress placed on the pins during the lead forming operation. While C-SAM and TDR had proven useful in the analysis of TSSOP packages, it can potentially be expanded to other wire-bonded packages.

In time domain reflectometry (TDR), the main emphasis lies on the reflected waveform. Poor probing contact is one of the common problems in getting an accurate waveform. TDR probe normalization is essential before measuring any TDR waveforms. The advantages of normalization include removal of test setup errors in the original test pulse and the establishment of a measurement reference plane. This article presents two case histories. The first case is about a Plastic Ball Grid Array package consisting of 352 solder balls where the open failure mode was encountered at various terminals after reliability assessment. In the second, a three-digit display LED suspected of an electrical short failure was analyzed using TDR as a fault isolation tool. TDR has been successfully used to perform non-destructive fault isolation in assisting the routine failure analysis of open and short failure. It is shown to be accurate and reduces the time needed to identify fault locations.

Time Domain Reflectometry (TDR) is an analysis technique for characterizing a transmission environment (PCB traces, cable assemblies, etc.) and identifying the physical location of defects or impedance discontinuities which can quickly narrow the focus of an investigation. This paper introduces the capability and presents several case studies spanning different applications where TDR was useful as a non-destructive analysis technique.

Space-domain reflectometry (SDR) utilizing scanning superconducting quantum interference device (SQUID) microscopy is a newly developed non-destructive failure analysis (FA) technique for open fault isolation. Unlike the conventional open fault isolation method, time-domain reflectometry (TDR), scanning SQUID SDR provides a truly two-dimensional physical image of device under test with spatial resolution down to 30 μm [1]. In this paper, the SQUID SDR technique is used to isolate dead open faults in flip-chip devices. The experimental results demonstrate the capability of SDR in open fault detection

Electro-optical terahertz pulse reflectometry (EOTPR) was introduced last year to isolate faults in advanced IC packages. The EOTPR system provides 10μm accuracy that can be used to non-destructively localize a package-level failure. In this paper, an EOTPR system is used for non-destructive fault isolation and identification for both 2D and 2.5D with TSV structure of flip-chip packages. The experimental results demonstrate higher accuracy of the EOTPR system in determining the distance to defect compared to the traditional time-domain reflectometry (TDR) systems.

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

The focus of this article is on locating signal-to-ground shorts and plane-to-plane shorts using the time domain reflectometry (TDR) based fault isolation system. The article proposes two comparative techniques for plane-to-plane short location, both based on the secondary information in the TDR data. The first technique looks for the difference in secondary reflections in the TDR waveform and the second looks at the inductance of the current return path, which can be computed in IConnect TDR software. The article presents simple test board example for plane-to-plane short failure location and discusses the results obtained by applying the TDR technique to the measurements of a sample package under test. Locating a signal-to-ground short has been shown to present little difficulty over a comparable open fault locating task. However, with the true impedance profile and planar inductance analyses, the claim of impossibility of locating a plane-to-plane is effectively challenged in this paper.

This paper describes the successful effort to develop the Time Domain Reflectometry (TDR) tool by automating the equipment process. The current challenges in the tool usage brought about by miniaturization in the package technology presented itself as an opportunity for the tool improvement. The authors were able to devise an automated TDR system which is ergonomically safe, yielded a significant through put time reduction and provide a consistent and accurate result. This comes at a lower cost in comparison to the current system available in the Virtual Factory (VF).

Time domain reflectometry (TDR) is increasingly being utilized as a failure analysis tool in the semiconductor industry. TDR can provide fast, nondestructive analysis of packaged integrated circuits. With one measurement, TDR analysis can provide instant identification of the general region of the fail site, whether it exists in the substrate, interconnect region, or in the die. A digital sampling oscilloscope with a TDR module supplies a fast risetime voltage edge to the signal pin of interest, and then records the subsequent voltage edge reflections. The time delay between the incident and reflected electrical signals are analyzed to characterize the electrical path of the signal pin. Initial implementation of TDR as an FA tool by the authors was in a comparative analysis method, where the TDR measurement from an unassembled substrate is used as the basis of comparison for the TDR measurement from the failing unit. Current development focuses on signature analysis of the TDR waveform for a given substrate path (including BGA substrate, flip-chip solder bump and pads, and flip-chip die). Interpretation of the TDR measurements for both comparative analysis and signature analysis of the TDR waveform will be discussed in this paper.

Electro Optical Terahertz Pulse Reflectometry (EOTPR), a terahertz based Time Domain Reflectometry (TDR) technique, has been evaluated on Flip Chip (FC) and 3D packages. The reduced size and complexity of these new generations of advanced IC products necessitate non-destructive techniques with increased fault isolation accuracy. The minimum accuracy achievable with conventional TDR is approximately 1000μm. Here, we show that EOTPR is able to differentiate all of the critical features in a 3D FC package, such as μC4 and Through Silicon Via (TSV), and is capable of producing distance-to-defect accuracy of less than 20μm, a significant improvement over conventional microwave based TDR techniques.

As integrated circuit packages become more complicated, the localization of defects becomes correspondingly more difficult. One particularly difficult class of defects to localize is high resistance (HR) defects. These defects include cracked traces, delaminated vias, C4 non-wet defects, PTH cracks, and any other package or interconnect structure that results in a signal line resistance change that exceeds the specification of the device. These defects can result in devices that do not run at full speed, are not reliable in the field, or simply do not work at all. The main approach for localizing these defects today is time domain reflectometry (TDR) [1]. TDR sends a short electrical pulse into the device and monitors the time to receive reflections. These reflections can correspond to shorts, opens, bends in a wire, normal interfaces between devices, or high resistance defects. Ultimately anything that produces an electrical impedance change will produce a TDR response. These signals are compared to a good part and require time consuming layer-by-layer deprocessing and comparison to a standard part. When complete, the localization is typically at best to within 200 microns. A new approach to isolating high resistance defects has been recently developed using current imaging. In recent years, current imaging through magnetic field detection has become a main-stream approach for short localization in the package [2] and is also heavily utilized for die level applications [3]. This core technology has been applied to the localization of high resistance defects. This paper will describe the approach, and give examples of test samples as well as results from actual yield failures.

The visual nature of Time Domain Reflectometry (TDR) makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This article discusses the use of TDR for package failure analysis work. It analyzes in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. The article examines the TDR measurement accuracy and the comparative package failure analysis, and presents three main considerations for package failure analysis. It also touches upon the goal and the task of the failure analysts and TDR's specific signatures for the open and short connections.

Traditional time domain reflectometry (TDR) techniques employ time-based information to locate faults within packages with minimal references to internal structures. Here, we combine a novel and innovative technique, electro optical terahertz pulse reflectometry (EOTPR) [1], with full 3D device-under-test (DUT) modelling to quickly and nondestructively perform feature-based analysis. We demonstrate fault isolation to an accuracy of 10 ìm or better with respect to device features in an advanced integrated circuit (IC) package.

Packages with the Modified Daisy-chain (MDC) die have been used increasingly to accelerate reliability stress testing of IC packaging during package development, qualification, and evaluation and reliability monitor programs [1]. Utilizing this approach in essence eliminates chip circuit failure mechanisms. Unlike packages with active die, in packages with the MDC die, when short occurred between two daisy-chain pairs of I/Os, there are four possibilities that can attribute to each pin of the two daisy-chain pairs. That makes the isolation of short failure difficult. Time Domain Reflectometry (TDR) is a well-described technique to characterize package discontinuity (open or short failure). By using a bare package substrate and a reference device, an analyst can characterize the discontinuity and localize it: within the package, the die-package interconnects, or on the die [2]. Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields generated by current. The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects [3]. In this paper, a new methodology that combines Resistance Analysis, TDR Isolation and SSM Identification for electrical debugging short in packages with the MDC die will be presented. Case studies will also be discussed.

This presentation provides an overview of the tools and techniques that can be used to analyze failures in semiconductor devices made with 3D technology. It assesses the current state of 3D technology and identifies common problems, reliability issues, and likely modes of failure. It compares and contrasts all relevant measurement techniques, including X-ray computed tomography, scanning acoustic microscopy (SAM), laser ultrasonics, ultrasonic beam induced resistance change (SOBIRCH), magnetic current imaging, magnetic field imaging, and magneto-optical frequency mapping (MOFM) as well as time domain reflectometry (TDR), electro-optical terahertz pulsed reflectometry (EOTPR), lock-in thermography (LIT), confocal scanning IR laser microscopy, infrared polariscopy, and photon emission microscopy (PEM). It also covers light-induced voltage alteration (LIVA), light-induced capacitance alteration (LICA), lock-in thermal laser stimulation (LI-TLS), and beam-based techniques, including voltage contrast (VC), electron-beam absorbed current (EBAC), FIB/SEM 3D imaging, and scanning TEM imaging (STEM). It covers the basic principles as well as advantages and limitations of each method.

Space Domain Reflectometry (SDR) is a newly developed non-destructive failure analysis (FA) technique for localizing open defects in both packages and dies through mapping in space domain the magnetic field produced by a radio frequency (RF) current induced in the sample, herein the name Space Domain Reflectometry. The technique employs a scanning superconducting quantum interference device (SQUID) RF microscope operating over a frequency range from 60 to 200 MHz. In this paper we demonstrate that SDR is capable of locating defective micro bumps in a flip-chip device.

This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

The growing popularity of 2.5D SSIT (Stacked Silicon Interconnect Technology) & 3D package technology in the IC industry had made it more challenging for manufacturers and packaging assembly sites to perform failure analysis and identifying the root causes of failures. There had been some technical papers written on various failure analysis techniques on 2.5D SSIT and 3D IC packages using a variety of equipment for detecting and localizing failures [1, 2]. This paper explains a non-evasive, non-destructive approach of localizing failures on a 2.5D SSIT package by identifying and recognizing certain waveform patterns that the failing devices exhibit in the scanning acoustic microscope A-Scan and in Time domain reflectometry. There are noticeable waveform patterns that an analyst can recognize and used to determine certain types of failure mechanisms that may be present in the device. Please note that it is very important to use the exact same type of package sample when characterizing and comparing waveform patterns as package variability from vendor to vendor and material contents can certainly affect the results.

Here, we demonstrate how electro optical terahertz pulse reflectometry (EOTPR) can be used to quickly and non-destructively isolate faults in 2.5D packages. We present case studies to show how EOTPR can unambiguously differentiate between faults located in the C4 bump, TSV, RDL, and micro-bump of a 2.5D package.

We combine Electro Optical Terahertz Pulse Reflectometry (EOTPR), with full three dimensional device-under-test (DUT) modeling utilizing virtual known good device to quickly and non-destructively isolate faults in advanced 3D IC packages. Computation power required for modeling can quickly become prohibitive with the design complexities of modern IC packages. In this study we adopt a piecemeal modeling approach that bypasses this exponential requirement. A PFA study verifies the accuracy of our model. This shows that feature-based fault analysis with a distance-to-defect accuracy of less than 10 μm can be readily attained through the combination of these techniques.